Abstract: An optical film, comprising a substrate, wherein a first plurality of multi-faceted recesses are formed on the substrate, wherein the plurality of multi-faceted recesses are capable of scattering lights that enter into a second surface of the substrate, said first surface and said second surface are two opposite surfaces of the substrate.

Abstract: A composite optical film, comprising: a quantum-dot film and a first optical film disposed over the quantum-dot film, wherein a first plurality of multi-faceted recesses are formed on a first surface of the first optical film, wherein each multi-faceted recess comprises a shape of a reversed cone.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a semiconductor channel layer, a gate dielectric layer, a source terminal and a drain terminal. The semiconductor channel layer is disposed over and above the gate. The gate dielectric layer is disposed between the gate and the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. A contact plug is disposed on at least one of the source terminal and the drain terminal. A dielectric pattern surrounds the contact plug and covers the source terminal and the drain terminal. A gas barrier layer is disposed on the dielectric pattern and surrounding the contact plug.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.

Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A droplet generator for an extreme ultraviolet imaging tool includes a reservoir for a molten metal, and a nozzle having a first end connected to the reservoir and a second opposing end where molten metal droplets emerge from the nozzle. A gas inlet is connected to the nozzle, and an isolation valve is at the second end of the nozzle configured to seal the nozzle droplet generator from the ambient.

Abstract: A semiconductor memory structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked over a substrate, and at least an active column disposed over the substrate. The gate layers and the insulating layers are alternately stacked along a first direction. The active column extends along the first direction and penetrates the gate layer and the insulating layer. The active column includes a central portion, a charge-trapping layer surrounding the central portion, and a channel layer between the central portion and the charge-trapping layer. The central portion of the active column includes an isolation structure, a source structure and a drain structure. The source structure and the drain structure are disposed at two sides of the isolation structure.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A method includes forming a plurality of memory cells, which includes a plurality of first conductive lines over a substrate, charge-trapping layers coupled to the conductive lines, channel layers arranged adjacent to the charge-trapping layers, and a plurality of first filling regions arranged between the channel layers; etching the first filling regions to form first trenches; depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches; forming second filling regions in the first trenches; patterning the second filling regions to form second trenches; depositing a partition region in each of the second trenches; and removing the liner to expose the charge-trapping layers and the channel layers.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

Abstract: A tridimensional memory cell array includes vertically stacked first conductive lines, vertically stacked second conductive lines, and first and second flights of steps. First and second conductive lines extend along a first direction. The second conductive lines are disposed at a distance along a second direction from the first conductive lines. First and second directions are orthogonal. Along the first direction, the first flights are disposed at opposite ends of the first conductive lines and the second flights are disposed at opposite ends of the second conductive lines. The first and second flights include landing pads and connective lines alternately disposed along the first direction. The landing pads are wider than the connective lines along the second direction. Along the second direction, landing pads of the first flights face connective lines of the second flights and landing pads of the second flights face connective lines of the first flights.

Abstract: A manufacturing method of a transformer includes: winding a first winding wire around a bobbin, wherein two ends of the first winding wire are connected to a first and a second pin of the bobbin respectively; winding a second winding wire around the bobbin, wherein two ends of the second winding wire are connected to a third and a fourth pin of the bobbin respectively; and winding a third and a fourth winding wire in parallel around the bobbin, wherein two ends of the third winding wire are connected to the second and a fifth pin of the bobbin respectively, and two ends of the fourth winding wire are connected to the fifth and a sixth pin respectively. The first, the third and the fourth winding wires form a primary coil, and the second winding wire is a secondary coil.

Abstract: A light guide structure with jagged protrusions is configured in a lighting device of a mobile vehicle. The light guide structure includes a light injecting surface and a light emitting surface. The light emitting surface includes a middle section and two side sections deployed respectively at opposite ends of the middle section. The side sections have a plurality of jagged protrusions forming a light guiding area. The extending direction of the jagged protrusions intersects with the light emitting direction. A light source module forms an irradiation area by the light guide structure, the light guiding area extending the width of both sides of the irradiation area, the beam contour being enlarged evenly. The disclosure also provides a headlight structure, a light source module having the light guide structure and a convex lens configured sequentially in the light emitting direction.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: Various embodiments of the present application are directed towards a memory cell, an integrated chip comprising a memory cell, and a method of operating a memory device. In some embodiments, the memory cell comprises a data-storage element having a variable resistance and a unipolar selector electrically coupled in series with the data-storage element. The memory cell is configured to be written by a writing voltage with a single polarity applying across the data-storage element and the unipolar selector.

Abstract: A first conductive pillar is formed. A plurality of second conductive pillars are formed at different sides of the first conductive pillar. A plurality of dielectric pillars are respectively formed between the first conductive pillar and the plurality of second conductive pillars. A channel layer is formed to continuously surround the first conductive pillar, the plurality of second conductive pillars and the plurality of dielectric pillars. A memory material layer is formed to surround the channel layer.