Patents by Inventor Chih Lin

Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220020951
    Abstract: Embodiments described herein relate to graded slope bottom reflective electrode layer structures for top-emitting organic light-emitting diode (OLED) display pixels. An EL device includes a pixel definition layer having a top surface, a bottom surface, and graded sidewalls interconnecting the top and bottom surfaces and a bottom reflective electrode layer disposed over the pixel definition layer. The bottom reflective electrode layer includes a planar electrode portion disposed over the bottom surface and a graded reflective portion disposed over the graded sidewalls, where the graded reflective portion has a concave profile. The EL device includes an organic layer disposed over the bottom reflective electrode layer and a top electrode disposed over the organic layer. Also described herein are methods for fabricating the EL device.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 20, 2022
    Inventors: Chung-Chia CHEN, Wan-Yu LIN, Gang YU, Byung-Sung KWAK, Robert Jan VISSER, Hyunsung BANG, Lisong XU, Chung-Chih WU, Hoang Yan LIN, Guo-Dong SU, YI-Jiun CHEN, Wei-Kai LEE
  • Publication number: 20220018009
    Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide-containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Inventors: Yuan-Chih Hsieh, Yi-Ren Wang, Hung-Hua Lin
  • Publication number: 20220019635
    Abstract: A method and a system for recommending personalized content, and a graphical user interface are provided. The method is operated in a serving system. When a user identification data is received from a user device, a user preference is acquired by querying a database, so as to match one or more digital contents that are consistent with the user preference. These digital contents are grouped according to locations of the digital contents. Multiple thumbnail images representing different groups of digital contents within a geographic range are generated. The thumbnail images are provided for the user device to display on the graphical user interface. The graphical user interface switches to the geographic range represented by the thumbnail image that is selected by a user. Multiple linking points are included in the geographic range, and the user selects one of the linking points to play corresponding digital content(s).
    Type: Application
    Filed: June 7, 2021
    Publication date: January 20, 2022
    Inventors: YU-HSIEN LI, YU-CHIH LEE, WEN-SHIANG LIN, SHI-TING LI, HAN-HSI HU, CHIA-YUAN CHENG
  • Patent number: 11229109
    Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Cheng
  • Publication number: 20220013403
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • Patent number: 11221712
    Abstract: A method of calibrating touch sensing applicable to a microprocessor of an ultrasonic touch sensing device, in which the ultrasonic touch sensing device is for generating a touch sensing signal according to a ultrasonic wave, and the method includes: receiving the touch sensing signal; measuring temperature of the ultrasonic touch sensing device to generate multiple temperature parameters; if a variation tendency of the temperature parameters is downward, and if a level of the touch sensing signal lower than a level of a reference signal is first detected, storing the level of the touch sensing signal as a first signal strength and reporting a touch event is detected; and if the variation tendency of the temperature parameters is downward, and if the level of the touch sensing signal lower than the level of the reference signal is not first detected, calibrating the reference signal according to the touch sensing signal.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: January 11, 2022
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution Limited
    Inventors: Fu-Cheng Wei, Chih-Lin Liao
  • Patent number: 11222784
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 11, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Patent number: 11222948
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a fin protruding from the front surface, the fin including: a first semiconductor layer in proximal to the front surface, a second semiconductor layer stacked over the first semiconductor layer, a gate between the first semiconductor layer and the second semiconductor layer, and a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region laterally surrounding the fin, wherein the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including: a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section, wherein an absolute value of a derivative at the third section is greater than an absolute value of a derivative at the second section.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
  • Patent number: 11222814
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Patent number: 11222788
    Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen Liao, Jun-Xiu Liu, Chun-Chih Lin
  • Publication number: 20220007501
    Abstract: A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Applicant: Super Micro Computer, Inc.
    Inventors: Manhtien V. PHAN, Mau-Lin CHOU, Chih-Hao LEE
  • Patent number: 11217900
    Abstract: An antenna structure suitable for 5G use in controlling direction of radio beams and in increasing antenna gain includes a substrate, an array of antennas, a main body, a lens array, a grounding plate, and a high-impedance surface (HIS) layer embedded into the substrate. The array of antenna units is positioned on the substrate surface under the protection of the main body. The lens array includes a lens units for each antenna unit, the lens units concentrate the beams generated by the antenna units. The grounding plate is underneath and grounds the antenna units. The HIS layer suppresses surface waves generated by the lens arrays and the substrate and increases a gain of the antenna structure in certain directions.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Zheng Lin, Yi-Ming Chen, Chih-Chung Hsieh, Ke-Jia Lin, Kuo-Cheng Chen
  • Patent number: 11217478
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Patent number: 11217732
    Abstract: The present invention provides a white light LED package structure and a white light source system, which includes a substrate, an LED chip, and a wavelength conversion material layer. The peak emission wavelength of the LED chip is between 400 nm and 425 nm; the peak emission wavelength of the wavelength conversion material layer is between 440 nm and 700 nm, and the wavelength conversion material layer absorbs light emitted from the LED chip and emits a white light source; and the emission spectrum of the white light source is set as P(?), the emission spectrum of a blackbody radiation having the same color temperature as the white light source is S(?), P(?max) is the maximum light intensity within 380-780 nm, S(?max) is the maximum light intensity of the blackbody radiation within 380-780 nm, D(?) is a difference between the spectrum of the white light LED and the spectrum of the blackbody radiation, and within 510-610 nm, the white light source satisfies: D(?)=P(?)/P(?max)?S(W)/S(?max), ?0.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 4, 2022
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Senpeng Huang, Junpeng Shi, Weng-Tack Wong, Shunyi Chen, Zhenduan Lin, Chih-Wei Chao, Chen-Ke Hsu
  • Patent number: 11217679
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
  • Patent number: 11217480
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210407993
    Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN
  • Publication number: 20210408311
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Inventors: Chu-Jih SU, Chia-Hsiang CHOU, Wei-Chih PENG, Wen-Luh LIAO, Chao-Shun HUANG, Hsuan-Le LIN, Shih-Chang LEE, Mei Chun LIU, Chen OU
  • Publication number: 20210403620
    Abstract: The invention discloses functionalized poly(2,6-dimethyl phenylene oxide oxide) oligomers containing dicyclopentadiene, a method of producing the same and use thereof. The cured products of the functionalized poly(2,6-dimethyl phenylene oxide oxide) oligomers of the invention exhibit low dielectric constant, low dissipation, and high glass transition temperature. As the functionalized poly(2,6-dimethyl phenylene oxide oxide) oligomers of the invention have number-average molecular weight ranging from 2500 to 6000 g/mol, the substrate made of theses functionalized poly(2,6-dimethyl phenylene oxide oxide) oligomers can pass the pressure cook test. Besides, the low dissipation factor characteristic the functionalized poly(2,6-dimethyl phenylene oxide oxide) oligomers of the invention can only be demonstrated at number-average molecular weight higher than 2500 g/mol.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Sheng-De Li, Ming-Yu Huang, Jui-Fu Kao, Way-Chih Hsu, Jann-Chen Lin, Yih-Ping Wang, Ching-Hsuan Lin
  • Publication number: 20210408338
    Abstract: A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength ?; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 30, 2021
    Inventors: Heng-Ying CHO, Li-Yu SHEN, Chih-Hao CHEN, Keng-Lin CHUANG