Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: Techniques for color change of Information elements (IEs) are described. In an example, a color of the IE and a color of a region of a virtual environment surrounding the IE may be compared. Based on the comparison, it may be determined whether the IE is distinguishable from the region of the virtual environment. Further, based on the determination, the color of the IE may be changed to facilitate distinguishability of the IE.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: A liquid intrusion detection device includes at least one circuit board, a plurality of liquid detection components, a multiplexer and a computing component. The plurality of liquid detection components are disposed on the at least one circuit board. The multiplexer is disposed on the at least one circuit board and has a plurality of output pins respectively connected to the plurality of liquid detection components. The computing component is disposed on the at least one circuit board and connected to the multiplexer, and is configured to switch the multiplexer to output a detection signal to one of the plurality of liquid detection components through one of the plurality of output pins, and output a liquid intrusion notification signal when a response signal of the detection signal meets a preset potential.

Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.

Abstract: Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

Abstract: An electronic device includes a housing, an antenna structure, and a feeding element. The antenna structure includes a grounding element, a feeding radiation element, a switching circuit, and a first parasitic radiation element. The feeding radiation element includes a feeding portion, a first radiating portion, a second radiating portion, a first grounding arm, and a second grounding arm. The feeding portion is connected between the first radiating portion and the second radiating portion. The first grounding arm and the second grounding arm are connected to the first radiating portion. The switching circuit is electrically connected to the first grounding arm and the second grounding arm. The first parasitic radiation element is connected to the grounding element and coupled with the feeding radiation element.

Abstract: A pre-roll circuit for an image sensing system is configured to receive a pre-stored image data through an image sensor and provide the pre-stored image data to a camera. The pre-roll circuit includes a first memory and a compressor circuit. The first memory is configured to store the pre-stored image data. The compressor circuit, coupled to the first memory, is configured to compress the pre-stored image data before the pre-stored image data is stored into the first memory.

Abstract: A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

Abstract: The present disclosure provides an organic light emitting display panel, a method for manufacturing the same, and an organic light emitting display apparatus. The organic light emitting display panel includes an array substrate, a color filter substrate and an encapsulation structure; the encapsulation structure includes a sealing frame and/or a sealing layer disposed between the array substrate and the color filter substrate, and the array substrate and the color filter substrate are adhesively fixed through the sealing frame and/or the sealing layer; wherein the sealing frame is formed by curing a frame sealant and is located in a frame area of the array substrate and the color filter substrate, and the sealing layer is formed by curing a filling adhesive and is located in a display area of the array substrate and the color filter substrate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.

Abstract: An airtight-level sensor includes an air pump, a sounding mechanism, and a processing device. The air pump comprises an inlet valve and an outlet valve, the sounding mechanism is disposed near the outlet valve to generate a sound wave corresponding to an airflow blown from the outlet valve, and the processing device is disposed near the sounding mechanism to receive the sound wave generated therefrom and determines an airtight-level of an airtight chamber wherein the airtight-level sensor is disposed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: The present disclosure relates to the field of display technology and provides a pixel array, a display panel and a metal mask. The pixel array includes a plurality of pixel units, and each pixel unit is composed of two red sub-pixels, two blue sub-pixels and a green sub-pixel. In each pixel unit, connection lines of centers of the red sub-pixels and the blue sub-pixels in a same row and a same column form a parallelogram, the two red sub-pixels and the two blue sub-pixels are located at diagonal positions of the parallelogram respectively, and a center of the green sub-pixel is located at an intersection position of diagonal lines of the parallelogram. Along the row direction, two adjacent parallelograms are in a translational relationship and share a column side. Along the column direction, two adjacent parallelograms are in a mirror-image relationship and share a row side.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels, that include hybrid thin-film transistor structures formed using semiconducting-oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. A drive transistor in the display pixel may be a top-gate semiconducting-oxide thin-film transistor and a switching transistor in the display pixel may be a top-gate silicon thin-film transistor. A storage capacitor in the display may include a conductive semiconducting-oxide electrode.