Patents by Inventor Chih-Lin LEE

Chih-Lin LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9955096
    Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Calvin Yi-Ping Chao, Shang-Fu Yeh, Chin-Hao Chang, Chih-Lin Lee, Kuo-Yu Chou, Chiao-Yi Huang
  • Publication number: 20180040606
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Publication number: 20170280086
    Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 28, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Calvin Yi-Ping CHAO, Shang-Fu YEH, Chin-Hao CHANG, Chih-Lin LEE, Kuo-Yu CHOU, Chiao-Yi HUANG