Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: A gray-scale driving method for a bi-stable chiral nematic liquid crystal display is provided. The present method divides an updated picture into a first-section frame, a second-section frame and a third-section frame. The present invented method includes to drive the first-section frame into a predetermined initial state, and drive the second-section frame by line-by-line scanning by writing updated gray-scale frame data into the pixels, then pull the third-section frame to zero voltage for the pixels such that bi-stable chiral nematic liquid crystal relaxes to stable states corresponding to the write-in gray-scale frame data. Meanwhile, a purpose to maintain the updated picture without any consumption of power is obtained. The total power consumption can be significantly reduced.

Abstract: Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by a forward biased p-n structure or a reverse biased p-n structure.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract: An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

Abstract: A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.

Abstract: An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.