Abstract: A printed circuit board and a method for fabricating the same is provided. A substrate having a core layer and a plurality of pairs of bond pads thereon is prepared with at least one opening formed on the core layer between each pair of the bond pads. A solder mask layer covers the core layer and fills the openings, with recessed portions formed at positions of the solder mask layer on the openings during curing of the solder mask layer. When a small passive component is mounted on the printed circuit board, a space is formed between the bottom of the passive component and the recessed portions of the solder mask layer. An encapsulating resin can flow into the space to form an insulating barrier between the bond pads to prevent bridging between the bond pads and short circuiting of the passive component.

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

Abstract: A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: A semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame includes a die pad and a plurality of leads properly spaced apart from the die pad, each lead being composed of an inner lead portion and an outer lead portion, wherein the inner lead portion is directed toward the die pad, and the outer lead portion has a terminal. At least a chip is mounted on the die pad, and a first encapsulant is formed for encapsulating the chip, die pad and inner lead portions. An injection-molded second encapsulant is formed for encapsulating the first encapsulant and outer lead portions, but exposing the terminals of the outer lead portions. The second encapsulant made by injection molding can prevent resin flash over the exposed terminals, thereby assuring electrical-connection quality of the semiconductor package.

Abstract: A window-type ball grid array (WBGA) semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame has a plurality of leads encompassing an opening, each lead having an upper surface and an opposing lower surface. A resin material is pre-molded on the lower surfaces of the leads, with wire-bonding portions and ball-implanting portions defined on the leads being exposed. At least a chip is mounted on the upper surfaces of the leads and covers the opening, allowing the chip to be electrically connected to the wire-bonding portions of the leads by a plurality of bonding wires via the opening. Then, an encapsulant is formed to encapsulate the chip and fill into the opening for encapsulating the bonding wires. Finally, solder balls are implanted on the ball-implanting portions of the leads to complete fabrication of the semiconductor package.

Abstract: A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.

Abstract: A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract: A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Abstract: A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

Abstract: The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plate has a top surface exposed outside a resin body used for encapsulating the chip and the heat sink, and a bottom surface opposed to the top surface. The planar plate further has a thick portion formed on the bottom surface relative to the position of the chip, wherein there is a gap formed between the end surface of the thick portion and the chip to prevent the heat sink from directly contacting with the chip, and an end surface of the thick portion has a plurality of flow channels formed along the flowing direction of the molding gate to avoid the formation of void in the gap so as to increase the yield rate of products.

Abstract: An improved method of preventing copper poisoning in the fabrication of metal interconnects on a semiconductor substrate comprises sequential formation of a copper layer, a first stop layer, a first inter-metal dielectric layer, a second stop layer, and a second inter-metal dielectric layer over the substrate. The second inter-metal dielectric layer and the second stop layer are defined to form an opening. A conformal first glue/barrier layer is formed over the substrate. The first glue/barrier layer and the first inter-metal dielectric layer are patterned to form a via hole below the opening until the first stop layer is exposed. Spacers are formed on sidewalls of the opening and the via hole below the opening. The first stop layer at bottom of the via hole is removed to expose the copper layer.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.