Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Abstract: A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

Abstract: A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Abstract: A spectroscopic overlay metrology system and corresponding spectroscopic overlay metrology methods are disclosed herein for improving overly measurement accuracy, optimizing overlay recipes, and/or minimizing (or eliminating) asymmetry-induced overly error from overlay measurements. An exemplary method includes generating a diffraction spectrum by an overlay target from incident radiation having more than one wavelength. The diffraction spectrum includes a plurality of positive ordered diffracted beams and a plurality of negative ordered diffracted beams that are separated by wavelength, such that the diffraction spectrum includes more than one wavelength of a positive order and a negative order.

Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.

Abstract: A structure in semiconductor fabrication includes at least a first periodic asymmetric feature and a periodic asymmetric second feature. The first feature contains a plurality of periodically distributed first elements. The first feature has a first asymmetric profile such that the first feature no longer has the same first asymmetric profile when it is rotated by 180 degrees. The second feature contains a plurality of periodically distributed second elements. The second feature has a second asymmetric profile such that the second feature no longer has the same second asymmetric profile when it is rotated by 180 degrees. The second asymmetric profile is different from the first asymmetric profile.

Abstract: A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.

Abstract: Provided is a method of characterizing photolithography lens quality. The method includes selecting an overlay pattern having a first feature with a first pitch and a second feature with a second pitch different than the first pitch, performing a photolithography simulation to determine a sensitivity coefficient associated with the overlay pattern, and providing a photomask having the overlay pattern thereon. The method also includes exposing, with a photolithography tool, a wafer with the photomask to form the overlay pattern on the wafer, measuring a relative pattern placement error of the overlay pattern formed on the wafer, and calculating a quality indicator for a lens in the photolithography tool using the relative pattern placement error and the sensitivity coefficient.

Abstract: A structure in semiconductor fabrication includes at least a first periodic asymmetric feature and a periodic asymmetric second feature. The first feature contains a plurality of periodically distributed first elements. The first feature has a first asymmetric profile such that the first feature no longer has the same first asymmetric profile when it is rotated by 180 degrees. The second feature contains a plurality of periodically distributed second elements. The second feature has a second asymmetric profile such that the second feature no longer has the same second asymmetric profile when it is rotated by 180 degrees. The second asymmetric profile is different from the first asymmetric profile.

Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.

Abstract: A method includes directing a beam of radiation along an optical axis toward a workpiece support, measuring a spectrum of the beam at a first time to obtain a first profile, measuring the spectrum of the beam at a second time to obtain a second profile, determining a spectral difference between the two profiles, and adjusting a position of the workpiece support along the optical axis based on the difference. A different aspect involves an apparatus having a workpiece support, beam directing structure that directs a beam of radiation along an optical axis toward the workpiece support, spectrum measuring structure that measures a spectrum of the beam at first and second times to obtain respective first and second profiles, processing structure that determines a difference between the two profiles, and support adjusting structure that adjusts a position of the workpiece support along the optical axis based on the difference.

Abstract: In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.

Abstract: Provided is a method of characterizing photolithography lens quality. The method includes selecting an overlay pattern having a first feature with a first pitch and a second feature with a second pitch different than the first pitch, performing a photolithography simulation to determine a sensitivity coefficient associated with the overlay pattern, and providing a photomask having the overlay pattern thereon. The method also includes exposing, with a photolithography tool, a wafer with the photomask to form the overlay pattern on the wafer, measuring a relative pattern placement error of the overlay pattern formed on the wafer, and calculating a quality indicator for a lens in the photolithography tool using the relative pattern placement error and the sensitivity coefficient.

Abstract: A method for overlay monitoring and control is introduced in the present disclosure. The method includes selecting a group of patterned wafers from a lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.

Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.

Abstract: A method includes directing a beam of radiation along an optical axis toward a workpiece support, measuring a spectrum of the beam at a first time to obtain a first profile, measuring the spectrum of the beam at a second time to obtain a second profile, determining a spectral difference between the two profiles, and adjusting a position of the workpiece support along the optical axis based on the difference. A different aspect involves an apparatus having a workpiece support, beam directing structure that directs a beam of radiation along an optical axis toward the workpiece support, spectrum measuring structure that measures a spectrum of the beam at first and second times to obtain respective first and second profiles, processing structure that determines a difference between the two profiles, and support adjusting structure that adjusts a position of the workpiece support along the optical axis based on the difference.

Abstract: A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first reflectivity and a second reflectivity of the irradiated overlay offset measurement target. The calculation unit is operable to determine an overlay offset using the detected first and second reflectivity by determining a predetermined overlay offset amount which provides an actual offset of zero.