Abstract: Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

Abstract: Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

Abstract: A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.

Abstract: A method of determining optical constants n and k for a film on a substrate is described. Optical measurements are preferably performed with an integrated optical measurement system comprising a reflectometer, spectral ellipsometer, and broadband spectrometer such as an Opti-Probe series tool from Therma-Wave. A beam profile reflectometer is employed to first determine the thickness of said film from a best fit of modeling data to experimental data. The thickness data is combined with the ellipsometer and spectrometer measurements to produce an experimental data output which is fitted with modeled information to determine a best fit of the data. Constants n and k are derived from the best fit of data. The method provides a higher accuracy for n and k values than by standard procedures which calculate n, k, and t simultaneously. The method may also be applied to bilayer or multi-layer film stacks.

Abstract: A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

Abstract: A system for measuring optical properties of a sample is provided. A light source provides incident polarized light. A detector detects reflected light from the sample surface. A processor determines a first coefficient (R) of the reflected light detected by the detector, determines a second coefficient (n), extinction coefficient (k), and thickness of the film based on the measured first coefficient, and determines a first dielectric constant (?1) and a second dielectric constant (?2) of the film according to the second coefficient (n) and extinction coefficient (k).

Abstract: A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

Abstract: A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

Abstract: A method and apparatus for improving a yield and throughput of a lithographic process track, the method including providing a first resist layer on a first process wafer; forming a first resist pattern in the first resist layer including a heating process according to a first temperature profile wherein the heating process comprises a plurality of temperature controllable heating zones; producing and collecting scattered light spectra from the first resist pattern processing the scattered light spectrum to obtain 3-dimensional information including first resist pattern critical dimensions; determining a second temperature profile for performing the heating process to achieve targeted resist pattern critical dimensions including a second resist pattern on a second process wafer; and, forming the second resist pattern dimensions including the heating process according to the second temperature profile.

Abstract: A methodology for doing process control by using a heating apparatus comprising heating zones is revealed. First, a target CD (critical dimension) map is assigned. A baseline CD map corresponding to a substrate processed with the heating apparatus at a baseline setting is also obtained. An original CD map corresponding to a substrate processed at an original setting is obtained. For each heating zone, a perturbed CD map corresponding to a substrate processed at a perturbed setting is also obtained. The temperature distribution of the heating apparatus is adjusted according to the error CD map defined by the baseline CD map and the target CD map, basis functions defined by the original CD map and perturbed CD maps, and expansion coefficients expanding the error CD map with basis functions.

Abstract: Provided are a system and method for modifying a fabrication process based on inline measurement information during manufacture of a semiconductor device. In one example, the method includes exposing a photoresist layer on the device, performing post-exposure baking on the photoresist layer, and obtaining at least one critical dimension (CD) measurement of the device. A determination may be made as to whether the CD measurement indicates that the exposure and/or baking step achieved a predefined result. If not, the device may be subjected to additional exposure or baking.

Abstract: A method and apparatus for scanning electron microscope measurements which maintains a constant e-beam dose to the surface of a wafer being measured and thereby maintains a constant resist shrinkage. The apparatus provides a magnetic lens, a movable wafer holder to adjust the distance between a wafer and the magnetic lens, an image detector, means to determine the distance between the wafer and the magnetic lens, a retarding voltage applied to the wafer holder, means to adjust the retarding voltage, and means to focus the magnetic lens. The apparatus also provides feedback systems between the movable wafer holder and the means to determine the distance between the wafer and the magnetic lens, between the image detector and the means to adjust the retarding voltage, and between the image detector and means to focus the magnetic lens so these adjustments can be made automatically. The method first sets the distance between the wafer and the magnetic lens.

Abstract: A method of determining optical constants n and k for a film on a substrate is described. Optical measurements are preferably performed with an integrated optical measurement system comprising a reflectometer, spectral ellipsometer, and broadband spectrometer such as an Opti-Probe series tool from Therma-Wave. A beam profile reflectometer is employed to first determine the thickness of said film from a best fit of modeling data to experimental data. The thickness data is combined with the ellipsometer and spectrometer measurements to produce an experimental data output which is fitted with modeled information to determine a best fit of the data. Constants n and k are derived from the best fit of data. The method provides a higher accuracy for n and k values than by standard procedures which calculate n, k, and t simultaneously. The method may also be applied to bilayer or multi-layer film stacks.

Abstract: Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.

Abstract: A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

Abstract: Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.

Abstract: A method for determining a surface charge state of a semiconductor wafer process surface including providing a semiconductor wafer having a process surface including patterned semiconductor features; positioning the semiconductor wafer in a scanning electron microscope (SEM) for imaging at least a portion of the process surface; adjusting an electron beam condition to produce an image of the at least a portion of the process surface including an electron beam Voltage; and, determining a Voltage present in the at least a portion of the process surface to determine a surface charge state of the process surface.

Abstract: A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

Abstract: Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.

Abstract: A method of forming an interconnect or metal line in a semiconductor device using an zinc activated metal surface and electroless deposition. The invention forms an active metal layer (e.g., Al) layer on an insulating layer in a via hole, activates the active metal layer to form a Zn layer, and electrolessly deposits a metal (e.g., Cu, Ni, Au, or Ag) by reacting with the Zn layer. The metal layer is electroless deposited over the insulating layer. The metal layer fills the via hole to form a metal interconnect or line. Key features of the invention are the active metal layer and the zincate process (not a zinc particle process).