Patents by Inventor Chih-Pin Hung
Chih-Pin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200083143Abstract: An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.Type: ApplicationFiled: September 10, 2019Publication date: March 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jung-Che TSAI, Ian HU, Chih-Pin HUNG
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Publication number: 20200066612Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.Type: ApplicationFiled: August 24, 2018Publication date: February 27, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Pin HUNG, Tang-Yuan CHEN, Jin-Feng YANG, Meng-Kai SHIH
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Patent number: 10553527Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.Type: GrantFiled: September 12, 2017Date of Patent: February 4, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Dao-Long Chen, Chih-Pin Hung
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Patent number: 10541198Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.Type: GrantFiled: January 30, 2018Date of Patent: January 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
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Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10535521Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: GrantFiled: March 8, 2019Date of Patent: January 14, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Patent number: 10522508Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.Type: GrantFiled: May 1, 2018Date of Patent: December 31, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ian Hu, Ming-Han Wang, Tsun-Lung Hsieh, Chih-Yi Huang, Chih-Pin Hung
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Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10515806Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: GrantFiled: March 8, 2019Date of Patent: December 24, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Publication number: 20190341368Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ian HU, Ming-Han WANG, Tsun-Lung Hsieh, Chih-Yi HUANG, Chih-Pin HUNG
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Publication number: 20190244909Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yong-Da CHIU, Shiu-Chih WANG, Shang-Kun HUANG, Ying-Ta CHIU, Shin-Luh TARNG, Chih-Pin HUNG
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206683Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the secType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20190206684Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, andType: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Publication number: 20190148326Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Pin HUNG, Dao-Long CHEN, Ying-Ta CHIU, Ping-Feng YANG
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Publication number: 20190127573Abstract: A polylactic acid resin composition includes about 100 parts by weight of a polylactic acid resin, about 0.001 to about 3 parts by weight of a nucleating agent and about 3 to about 70 parts by weight of a filler. The polylactic acid resin composition can be processed into a biodegradable molded article or other product having a high impact strength and a high heat deflection temperature.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chean-Cheng SU, Chih-Pin HUNG, Shin-Luh TARNG, Chaung Chi WANG, Chao Ming TSENG, Shiu-Chih WANG
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Semiconductor device packages and stacked package assemblies including high density interconnections
Patent number: 10276382Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: GrantFiled: June 6, 2017Date of Patent: April 30, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang -
Publication number: 20190103386Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: William T. CHEN, John Richard HUNT, Chih-Pin HUNG, Chen-Chao WANG, Chih-Yi HUANG
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Patent number: 10236208Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.Type: GrantFiled: June 16, 2016Date of Patent: March 19, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Cheng Kuo, Pao-Nan Lee, Chih-Pin Hung, Ying-Te Ou
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Publication number: 20190080993Abstract: A substrate including a dielectric layer and a patterned conductive layer adjacent to the dielectric layer is provided. The patterned conductive layer comprises a first conductive pad, the first conductive pad comprises a first portion having a first concave sidewall. The substrate further includes a protection layer disposed on the patterned conductive layer, and the protection layer covers the first portion of the first conductive pad.Type: ApplicationFiled: September 12, 2017Publication date: March 14, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Dao-Long CHEN, Chih-Pin HUNG
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Patent number: 10217649Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.Type: GrantFiled: June 9, 2017Date of Patent: February 26, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jin-Yuan Lai, Tang-Yuan Chen, Ying-Xu Lu, Dao-Long Chen, Kwang-Lung Lin, Chih-Pin Hung, Tse-Chuan Chou, Ming-Hung Chen, Chi-Hung Pan
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Patent number: 10181448Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: GrantFiled: March 22, 2016Date of Patent: January 15, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Pin Hung, Dao-Long Chen, Ying-Ta Chiu, Ping-Feng Yang
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Publication number: 20180358238Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Inventors: Jin-Yuan LAI, Tang-Yuan CHEN, Ying-Xu LU, Dao-Long CHEN, Kwang-Lung LIN, Chih-Pin HUNG, Tse-Chuan CHOU, Ming-Hung CHEN, Chi-Hung PAN