Abstract: A circuit board with reduced simultaneous switching noise. The circuit board comprises a first conductor plane with a first fixed potential, a dielectric layer, at least a build-up via and a second conductor plane with a second fixed potential. The dielectric layer is formed on the first conductor plane. The build-up vias are formed in the dielectric layer and filled with a conductive material. The second conductor plane is in contact with the conductive material in the build-up vias. The depth of the build-up vias is less than one fourth of a signal wavelength.

Abstract: An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.

Abstract: A package for being electrically connected to an external printed wiring board and an external electronic device comprises a substrate, a semiconductor chip, a mold compound, and a connector. The substrate is electrically connected to the external printed wiring board. The semiconductor chip is disposed on and electrically connected to the substrate. The molding compound is used for encapsulating the semiconductor chip. The connector is disposed on the substrate for electrically connecting the semiconductor chip to the external electronic device.

Abstract: A flip-chip package substrate with a high-density layout. A number of pads and a number of traces are formed on an upper surface of the substrate. At least a pad has a short axis and a vertical long axis which are perpendicular to each other. The distance between the elongated pad and the pad adjacent thereto is not smaller than two thirds of the length of the short axis, so that at least two of the traces can pass between the elongated pad and the pad adjacent thereto.

Abstract: A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.

Abstract: A package structure with an area bump has at least a chip (also known as a die), a substrate, a plurality of first bumps (normal bumps) and at least a second bump (area bump), wherein the first bumps are electrically and mechanically connected to one of first bonding pads and the corresponding one of first contact pads. The second bump is electrically and mechanically connected to a second bonding pad and the corresponding second contact pad of the substrate, wherein the size of the second bump is larger than one of the first bumps. Because the size of the second bump is larger than one of the first bumps, the structure has much better electrical performance and performance of heat dissipation.

Abstract: A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.

Abstract: An MCM package with bridge connection mainly comprises a carrier, a first chip, a second chip and at least one conductive body. The carrier has an upper surface and an opposite lower surface, and a plurality of contacts formed on the upper surface of the carrier. The first chip has a first active surface, a first side surface and a first boding pad formed on the first active surface. Similarly, the second chip has a second active surface, a second side surface, and a second boding pad formed on the second active surface. Therein, the first side surface of the first chip is proximate to the second side surface of the second chip, and the first active surface is coplanar to the second active chip. Accordingly, one of the conductive body can be disposed continuously on the active surface and the second surface to electrically connect the first chip and the second chip.

Abstract: The present invention relates to a packaging mold with electrostatic discharge protection, comprising at least one recess for receiving at least one packaging substrate, the packaging substrate comprising an outer wall with a first height, the recess comprising an inner wall with a second height and the inner wall electrically connecting the outer wall of the packaging substrate, wherein the second height is larger than the first height. When separating the packaging substrate and the packaging mold, the duration of the outer wall connecting to the inner wall is extended, so that static electric charges generated when separating are conducted via the packaging mold preventing the dice to be packaged from damage due to electrostatic discharge to raise the yield rate of semiconductor package products thereby.

Abstract: A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.

Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

Abstract: A structure of flip chip package with an area bump has at least a chip (also known as a die), a substrate, a plurality of first bumps (normal bumps) and at least a second bump (area bump), wherein the first bumps are electrically and mechanically connected to one of first bonding pads and the corresponding one of first contact pads. The second bump is electrically and mechanically connected to a second bonding pad and the corresponding second contact pad of the substrate, wherein the size of the second bump is larger than one of the first bumps. Because the size of the second bump is larger than one of the first bumps, the structure has much better electrical performance and performance of heat dissipation.

Abstract: A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.

Abstract: An MCM package with bridge connection mainly comprises a carrier, a first chip, a second chip and at least one conductive body. The carrier has an upper surface and an opposite lower surface, and a plurality of contacts formed on the upper surface of the carrier. The first chip has a first active surface, a first side surface and a first boding pad formed on the first active surface. Similarly, the second chip has a second active surface, a second side surface, and a second boding pad formed on the second active surface. Therein, the first side surface of the first chip is proximate to the second side surface of the second chip, and the first active surface is coplanar to the second active chip. Accordingly, one of the conductive body can be disposed continuously on the active surface and the second surface to electrically connect the first chip and the second chip.

Abstract: A structure of flip chip package with an area bump has at least a chip (also known as a die), a substrate, a plurality of first bumps (normal bumps) and at least a second bump (area bump), wherein the first bumps are electrically and mechanically connected to one of first bonding pads and the corresponding one of first contact pads. The second bump is electrically and mechanically connected to a second bonding pad and the corresponding second contact pad of the substrate, wherein the size of the second bump is larger than one of the first bumps. Because the size of the second bump is larger than one of the first bumps, the structure has much better electrical performance and performance of heat dissipation.

Abstract: A package for being electrically connected to an external printed wiring board and an external electronic device comprises a substrate, a semiconductor chip, a mold compound, and a connector. The substrate is electrically connected to the external printed wiring board. The semiconductor chip is disposed on and electrically connected to the substrate. The molding compound is used for encapsulating the semiconductor chip. The connector is disposed on the substrate for electrically connecting the semiconductor chip to the external electronic device.

Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.

Abstract: A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.

Abstract: The present invention relates to a packaging mold with electrostatic discharge protection, comprising at least one recess for receiving at least one packaging substrate, the packaging substrate comprising an outer wall with a first height, the recess comprising an inner wall with a second height and the inner wall electrically connecting the outer wall of the packaging substrate, wherein the second height is larger than the first height. When separating the packaging substrate and the packaging mold, the duration of the outer wall connecting to the inner wall is extended, so that static electric charges generated when separating are conducted via the packaging mold preventing the dice to be packaged from damage due to electrostatic discharge to raise the yield rate of semiconductor package products thereby.

Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.