Abstract: An image sensor device includes a substrate having a pixel array region, isolation structures in the substrate separating pixel regions from one another in the pixel array region, a photo-sensing region in each of the pixel regions, and a reflective cavity structure in the substrate within each of the pixel region. The reflective cavity structure continuously extends from a bottom of the isolation structure to a deeper central portion of each of the pixel regions, thereby forming a dish-like profile. The reflective cavity structure has a reflective index smaller than that of the substrate.

Abstract: An image sensor device includes a substrate having a pixel array region, isolation structures in the substrate separating pixel regions from one another in the pixel array region, a photo-sensing region in each of the pixel regions, and a reflective cavity structure in the substrate within each of the pixel region. The reflective cavity structure continuously extends from a bottom of the isolation structure to a deeper central portion of each of the pixel regions, thereby forming a dish-like profile. The reflective cavity structure has a reflective index smaller than that of the substrate.

Abstract: A manufacturing method of a non-volatile memory is provided. A tunneling dielectric layer, a first conductive pattern, and isolation structures are formed on a substrate. Using a first photoresist layer as a mask, the first conductive pattern is partially removed to form a first opening exposing the substrate. An insulating layer is formed to fill the first opening and cover the first conductive pattern and the isolation structures. Using a second photoresist layer shielding a portion of the first conductive pattern as a mask, the insulating layer surrounding the first conductive pattern is removed to form a patterned insulating layer having a second opening exposing a portion of the first conductive pattern. An inter-gate dielectric layer and a second conductive pattern are formed on the first conductive pattern to fill the second opening, the first conductive pattern forms a floating gate, and the second conductive pattern forms a control gate.

Abstract: A manufacturing method of a non-volatile memory is provided. A tunneling dielectric layer, a first conductive pattern, and isolation structures are formed on a substrate. Using a first photoresist layer as a mask, the first conductive pattern is partially removed to form a first opening exposing the substrate. An insulating layer is formed to fill the first opening and cover the first conductive pattern and the isolation structures. Using a second photoresist layer shielding a portion of the first conductive pattern as a mask, the insulating layer surrounding the first conductive pattern is removed to form a patterned insulating layer having a second opening exposing a portion of the first conductive pattern. An inter-gate dielectric layer and a second conductive pattern are formed on the first conductive pattern to fill the second opening, the first conductive pattern forms a floating gate, and the second conductive pattern forms a control gate.

Abstract: A CMOS image sensor unit and a method for fabricating the same are described. The image sensor unit includes a photodiode, a transfer gate, a reset gate, a source follower gate, a floating drain region between the transfer gate and the reset gate, and a PIP capacitor. The lower poly-Si electrode of the PIP capacitor is electrically connected with the floating drain region and the source follower gate to also serve as an interconnect between the floating drain region and the source follower gate. The fabrication method includes forming contact plugs on the floating drain region and the source follower gate, and then forming a PIP capacitor whose lower poly-Si electrode is connected with each contact plug.

Abstract: An image sensor includes a semiconductor substrate having a main surface, a transfer transistor having a transfer gate disposed on the main surface, a light-sensing structure on one side of the transfer gate, a floating diffusion node on the other side of the transfer gate, a reset transistor serially connected to the transfer transistor via the floating diffusion node, a source-follower transistor having a source-follower gate, and a vertical capacitor having a first vertical electrode plate and a second vertical electrode plate. The first vertical electrode plate is electrically connected to the source-follower gate and the floating diffusion node.

Abstract: An image sensor device includes a substrate having a first conductivity type. A plurality of photo-sensing regions including a first, a second, and a third photo-sensing regions corresponding to the R, G, B pixels are provided on the substrate. An insulation structure is disposed on the substrate to separate the photo-sensing regions from one another. A photodiode structure is formed within each photo-sensing region. A deep well structure having a second conductivity type. The deep well structure only overlaps with the second and third photo-sensing regions. The deep well structure does not overlap with the first photo-sensing region.

Abstract: A manufacturing method of an image sensor is provided. A substrate is provided, and the substrate includes a pixel array region. A plurality of openings is formed in the pixel array region of the substrate. A light guide region is formed in the substrate aside each of the openings, wherein a portion of the substrate is disposed between the light guide region and the opening, and the depth of the light guide region in the substrate is greater than the depth of the opening aside the light guide region in the substrate. Isolation structures are formed in the openings to define a plurality of pixel regions respectively located between two adjacent isolation structures in the pixel array region. A photosensitive region is formed in each of the pixel regions of the substrate. A conductive line layer is formed on each of the pixel regions of the substrate.

Abstract: A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression.

Abstract: The present invention relates to an electrical connector for fastening a flexible flat cable. The electrical connector includes an insulating body, a plurality of terminals, a pair of shims and a flip cover. The flip cover has rotatable portions pivotally disposed within the guiding grooves of the terminals, which enable the flip cover to rotate between a position for an open loop and a position for a closed loop. When the flip cover is in the position for an open loop, the rotatable portions are embedded into the guiding grooves. When the flip cover is in the position for a closed loop, the rotatable portions are propped against the upper arms and the lower arms simultaneously such that the upper contact portions are propped downwards tightly against the flexible flat cable to securely hold and position the flexible flat cable.

Abstract: The present invention relates to an electrical connector for fastening a flexible flat cable. The electrical connector includes an insulating body, a plurality of terminals, a pair of shims and a flip cover. The flip cover has rotatable portions pivotally disposed within the guiding grooves of the terminals, which enable the flip cover to rotate between a position for an open loop and a position for a closed loop. When the flip cover is in the position for an open loop, the rotatable portions are embedded into the guiding grooves. When the flip cover is in the position for a closed loop, the rotatable portions are propped against the upper arms and the lower arms simultaneously such that the upper contact portions are propped downwards tightly against the flexible flat cable to securely hold and position the flexible flat cable.

Abstract: The present invention discloses a flexible flat cable connector comprising an insulating body, a plurality of conductive terminals and a cover. The conductive terminals are inserted into the terminal grooves of the insulating body, and the cover is assembled on the top of the containing space of the insulating body. The first switch terminal and the second switch terminal are disposed in the insulating body, and the first switch terminal is located above the second switch terminal. When a flexible flat cable which has a lobe located at the one side is inserted into the containing space, the lobe of the flexible flat cable can contact against on the first switch terminal which then presses downwardly to the second switch terminal so as to detect whether or not the flexible flat cable is correctly positioned, and cause the flexible flat cable to conduct with the conductive terminal.

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A method for preparing a flash memory structure comprises the steps of forming a plurality of dielectric blocks having block sidewalls on a substrate, forming a plurality of first spacers on the block sidewalls of the dielectric blocks, removing a portion of the substrate not covered by the dielectric blocks and the first spacers to form a plurality of trenches in the substrate, performing a deposition process to form an isolation dielectric layer filling the trenches, removing the dielectric blocks to expose spacer sidewalls of the first spacers, forming a plurality of second spacers on the spacer sidewalls of the first spacers, and removing a portion of the substrate not covered by the first spacers, the second spacers and the isolation dielectric layer to form a plurality of second trenches in the substrate.

Abstract: The present invention discloses a flexible flat cable connector comprising an insulating body, a plurality of conductive terminals and a cover The conductive terminals are inserted into the terminal grooves of the insulating body, and the cover is assembled on the top of the containing space of the insulating body. The first switch terminal and the second switch terminal are disposed in the insulating body, and the first switch terminal is located above the second switch terminal. When a flexible flat cable which has a lobe located at the one side is inserted into the containing space, the lobe of the flexible flat cable can contact against on the first switch terminal which then presses downwardly to the second switch terminal so as to detect whether or not the flexible flat cable is correctly positioned, and cause the flexible flat cable to conduct with the conductive terminal.

Abstract: A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers.

Abstract: A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells. The aspect ratio of the gap between the cells is about 1.8 to 3.2. Many advantages are provided with such NAND flash memory fabricating by the self-aligned process of the present invention.

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract: A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.