Method for producing a memory with high coupling ratio
A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.
The present application is based on, and claims priority from, Taiwan Application Serial Number 94130391, filed Sep. 5, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.
BACKGROUND1. Field of Invention
The present invention relates to a method for producing a memory. More particularly, the present invention relates to a method for producing a memory with high coupling ratio.
2. Description of Related Art
Memory-related technology is progressing rapidly. Because of the high market demand for lighter, thinner and smaller products, flash memory is extensively used and has become a main nonvolatile memory nowadays. Because the physical size of the memory is becoming smaller and smaller, the size of each memory cell within the memory structures also must be made smaller, which results in decreasing the overlapping area of a floating gate and a control gate in each memory cell. Therefore, the coupling ratio of the floating gate and the control gate decreases. Because of low coupling ratio, the memory requires a higher voltage applied on its control gate to function. Not only the efficiency of the memory but also the reliability of the memory becomes less over a long time. Moreover, the conventional memory has a serious parasitic transistor effect that is described in detail below.
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It is therefore an aspect of the present invention to provide a method for producing a memory. The memory has high coupling ratio, the memory thus can read and write data faster.
Another aspect of the present invention relates to a method for producing a memory structure, wherein a concave portion is not formed on the edge of shallow trench isolation during wet etching process, and thus electric leakage is reduced.
In accordance with the foregoing aspects, one embodiment of the present invention provides a method for producing a memory. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.
Since the spacer protects the edge of the shallow trench isolation from being etched and from being concave portiond in the etching process, electric leakage does not occur when the memory is functioning. Furthermore, the fact that the top of the spacer is higher than the surface of the shallow trench isolation results in a curvature on the surface of the floating gate when the floating gate is formed on the substrate. The surface area of the floating gate is therefore increased, which allows a greater overlapping area between the floating gate and the control gate and increases the coupling ratio of the memory structure. Accordingly, the memory of the present invention can function more efficiently and is more reliable.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings as follows:
The memory structure described herein is mainly a nonvolatile memory, particularly a flash memory. A flash memory is exemplified below to illustrate the characteristics and the concept of the present invention.
A flash memory is composed of a plurality of memory cells. Each of the memory cells is isolated by an isolation structure. In a preferred embodiment of the present invention, the isolation structure is a shallow trench isolation. Since each memory cell has the same structure, the description below only describes the structure of a single memory cell.
Reference is made to
In a preferred embodiment of the present invention, the removal of the pad oxide 203 and the reduction of the height of the shallow trench isolation 206 are performed by isotropic etching, preferably by a wet etching. The solution for the wet etching can be hydrofluoric acid, diluted hydrofluoric acid or buffered hydrofluoric acid, which is determined according to the required quality and etching rate.
In another embodiment of the present invention, the memory cell is formed by sequentially depositing a polysilicon layer, a gate dielectric layer and a polysilicon layer, and then performing lithography and etching processes to define the floating gate 208, the gate dielectric 212, and the control gate 214.
The term “coupling ratio” is used to indicate the overlapping area of the control gate 214 with the floating gate 208. As the coupling ratio increases, the operation efficiency of memory is improved and the memory can be erased at a higher speed. Generally, the coupling ratio can be increased by the thickness reduction of the gate dielectric 212. However, increasing the coupling ratio by this method is limited since the thickness of the gate dielectric 212 generally ranges from a minimum of 80 Å to 90 Å.
In the memory structure of the preferred embodiment, the top of the spacer 210 is higher than the upper surface of the shallow trench isolation 206. When the floating gate 208 is formed on the spacer, the surface of the floating gate 208 is rippled and thus the surface areas of the floating gate 208, the gate dielectric 212 and the control gate 214 thereon are also increased. Therefore, the overlapping area between the floating gate 208 and the control gate 214 is increased, and the coupling ratio is increased.
Accordingly, the present invention has the following advantages.
(1) The memory of the embodiment comprises a spacer to protect the edge of the shallow trench isolation so that a problem of corner oxide thinning that usually occurs in the concave portion at the sidewall of the shallow trench isolation can be avoided. Also, no unwanted materials are left in the concave portion, and thus electric leakage is reduced.
(2) The memory of the embodiment has high coupling ratio, and thus has better efficiency and higher reliability.
The preferred embodiments of the present invention described above should not be regarded as limitations to the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention. The scope of the present invention is as defined in the appended claims.
Claims
1. A method for producing a memory cell, the method comprising:
- forming a shallow trench isolation in a substrate to define an active area;
- forming a spacer at a sidewall of the shallow trench isolation;
- etching the shallow trench isolation such that a top of the spacer is higher than an upper surface of the shallow trench isolation;
- forming a tunnel oxide on the active area; and
- forming a floating gate on the tunnel oxide.
2. The method for producing a memory cell of claim 1, wherein the step of forming the spacer comprises:
- depositing a spacer material layer on the substrate; and
- anisotropically etching the spacer material layer to form the spacer.
3. The method for producing a memory cell of claim 2, wherein the step of depositing a spacer material layer is performed by a chemical vapor deposition process or a high temperature oxidation process.
4. The method for producing a memory cell of claim 2, wherein the anisotropic etching is a dry etching.
5. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon nitride.
6. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon oxynitride.
7. The method for producing a memory cell of claim 2, wherein the spacer material layer is silicon oxide having an etching rate slower than the shallow trench isolation.
8. The method for producing a memory cell of claim 2, wherein the spacer material layer is doped polysilicon.
9. The method for producing a memory cell of claim 1, further comprising:
- forming a gate dielectric on the floating gate; and
- forming a control gate on the gate dielectric.
10. A method for producing a memory, the method comprising:
- forming a shallow trench isolation in a substrate;
- forming a spacer at a sidewall of the shallow trench isolation, wherein a top of the spacer is higher than an upper surface of the shallow trench isolation;
- forming a tunnel oxide on the substrate;
- forming a floating gate on the tunnel oxide and the spacer;
- forming a gate dielectric on the floating gate; and
- forming a control gate on the gate dielectric.
11. The method for producing a memory of claim 10, wherein the step of forming the spacer comprises:
- depositing a spacer material layer on the substrate;
- etching the spacer material layer to form the spacer at the sidewall of the shallow trench isolation; and
- lowering a height of the shallow trench isolation such that the top of the spacer is higher than the upper surface of the shallow trench isolation
12. The method for producing a memory of claim 11, wherein the step of lowering the height of the shallow trench isolation comprises performing a wet etching process to remove the material on the top of the shallow trench isolation.
13. The method for producing a memory of claim 10, wherein the material of the spacer is silicon nitride.
14. The method for producing a memory of claim 10, wherein the material of the spacer is silicon oxide with an etching rate slower than the material of the shallow trench isolation.
15. The method for producing a memory of claim 10, wherein the step of forming a shallow trench isolation comprises:
- forming a shallow trench in a substrate;
- forming a liner layer on an inner surface of the shallow trench; and
- filling a dielectric material in the shallow trench.
Type: Application
Filed: Nov 15, 2005
Publication Date: Mar 8, 2007
Inventors: Chih-Ping Chung (Linluo Township), Chun-Nan Lin (Changhua City), Chung-Yi Chen (Jhonghe City), Hung-Kwei Liao (Longtan Township)
Application Number: 11/272,685
International Classification: H01L 21/336 (20060101);