Patents by Inventor Chih-Sen Huang

Chih-Sen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840111
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 10787408
    Abstract: A method for producing 9,9-bis(3-phenyl-4-(2-hydroxyethoxy)phenyl)fluorene is provided. The method includes the steps of: performing a condensation reaction with fluorenone and 2-[(2-phenyl)phenoxy]ethanol in the presence of a catalyst and co-catalyst, wherein the catalyst is alkylsulfonic acid, and the co-catalyst is a mercapto-containing compound, thereby effectively reducing the formation of a by-product, such that the product has characteristics of low chroma, high purity, and high yield.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 29, 2020
    Assignee: CHINA PETROCHEMICAL DEVELOPMENT CORPORATION
    Inventors: Ding-Chi Huang, Yu-Sen Chen, Chih-Wei Chang, Wei-Ying Li
  • Publication number: 20200131110
    Abstract: The present disclosure provides a method for preparing o-phenyl phenoxyalkyl acrylate, including: transesterifying an acrylate-based compound with a biphenyl alcohol compound in the absence of a solvent and in the presence of a catalyst and a polymerization inhibitor to prepare the o-phenyl phenoxyalkyl acrylate represented by the following formula (II), wherein the catalyst is a compound containing a tin element or a titanium element. According to the method of the present disclosure, the o-phenyl phenoxyalkyl acrylate having transparency and high refractive index can be obtained. Moreover, the method of the present disclosure has the characteristics of high conversion rate and high selectivity, and does not need to add other organic solvents, so that many purification processes can be saved, and the production cost is effectively reduced, which has the value of industrial application.
    Type: Application
    Filed: June 20, 2019
    Publication date: April 30, 2020
    Applicant: China Petrochemical Development Corporation, Taipei (Taiwan)
    Inventors: Yu-Sen Chen, Min-Chia Huang, Yu-Chiao Liu, Chih-Wei Chang
  • Patent number: 10633325
    Abstract: The present disclosure provides a method for preparing o-phenyl phenoxyalkyl acrylate, including: transesterifying an acrylate-based compound with a biphenyl alcohol compound in the absence of a solvent and in the presence of a catalyst and a polymerization inhibitor to prepare the o-phenyl phenoxyalkyl acrylate represented by the following formula (II), wherein the catalyst is a compound containing a tin element or a titanium element. According to the method of the present disclosure, the o-phenyl phenoxyalkyl acrylate having transparency and high refractive index can be obtained. Moreover, the method of the present disclosure has the characteristics of high conversion rate and high selectivity, and does not need to add other organic solvents, so that many purification processes can be saved, and the production cost is effectively reduced, which has the value of industrial application.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 28, 2020
    Assignee: China Petrochemical Development Corporation, Taipei (Taiwan)
    Inventors: Yu-Sen Chen, Min-Chia Huang, Yu-Chiao Liu, Chih-Wei Chang
  • Patent number: 10600882
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: March 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Patent number: 10553576
    Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 ?m to 5 ?m and a second length along Y-direction between 3 ?m to 5 ?m.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20190196098
    Abstract: An optical waveguide includes a lower clad layer, a core layer, and an upper clad layer, wherein the core layer is disposed between the lower clad layer and the upper clad layer. The lower clad layer has a composition including unetchable closed-loop polyimide and plate-shaped clay in a range of 20 wt %-60 wt %. The core layer has a composition including etchable closed-loop polyimide and plate-shaped clay in a range of 20 wt %-60 wt %. The upper clad layer has a composition including an organic material and plate-shaped clay in a range of 20 wt %-60 wt %. The core layer has a refractive index lager than that of the upper clad layer and the lower clad layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: June 27, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Jen YANG, Li-Ting HUANG, Dong-Sen CHEN, Chyi-Ming LEU
  • Patent number: 10310179
    Abstract: An optical waveguide includes a lower clad layer, a core layer, and an upper clad layer, wherein the core layer is disposed between the lower clad layer and the upper clad layer. The lower clad layer has a composition including unetchable closed-loop polyimide and plate-shaped clay in a range of 20 wt %-60 wt %. The core layer has a composition including etchable closed-loop polyimide and plate-shaped clay in a range of 20 wt %-60 wt %. The upper clad layer has a composition including an organic material and plate-shaped clay in a range of 20 wt %-60 wt %. The core layer has a refractive index lager than that of the upper clad layer and the lower clad layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 4, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Jen Yang, Li-Ting Huang, Dong-Sen Chen, Chyi-Ming Leu
  • Patent number: 10199374
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 10141263
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Patent number: 10049929
    Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 14, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Patent number: 10026726
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Publication number: 20180174970
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 21, 2018
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Publication number: 20180166441
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Application
    Filed: November 28, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Publication number: 20180166434
    Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 ?m to 5 ?m and a second length along Y-direction between 3 ?m to 5 ?m.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 14, 2018
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9984974
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9985020
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9985123
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Wei-Hao Huang
  • Publication number: 20180130742
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9941215
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang