Patents by Inventor Chih-Sheng Chang

Chih-Sheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127675
    Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Publication number: 20210288138
    Abstract: A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.
    Type: Application
    Filed: April 30, 2020
    Publication date: September 16, 2021
    Inventors: Bo-Wei HUANG, Chun-Wei KANG, Ho-Yu LAI, Chih-Sheng CHANG
  • Patent number: 11114540
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Publication number: 20210210636
    Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Inventors: Hung-Li Chiang, Chih-Sheng Chang, Tzu-Chiang Chen
  • Patent number: 11056401
    Abstract: A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
  • Publication number: 20210202743
    Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.
    Type: Application
    Filed: March 10, 2021
    Publication date: July 1, 2021
    Inventors: Kuo-Cheng Chiang, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Publication number: 20210193575
    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Chen-Yi Weng, Shih-Che Huang, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 11043489
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Patent number: 11037835
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Publication number: 20210175129
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 10, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Publication number: 20210175342
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Inventors: Chun-Chieh LU, Cheng-Yi PENG, Chien-Hsing LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Publication number: 20210159170
    Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 27, 2021
    Inventors: Min-Shiang Hsu, Yu-Han Tsai, Chih-Sheng Chang
  • Publication number: 20210151321
    Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 20, 2021
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Publication number: 20210118997
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Patent number: 10978391
    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Yi Weng, Shih-Che Huang, Ching-Li Yang, Chih-Sheng Chang
  • Publication number: 20210096286
    Abstract: A diffractive optical element and method for fabricating the diffractive optical element are provided. The diffractive optical element includes a substrate, a first diffractive structure layer and a second diffractive structure layer. The substrate has a first surface and a second surface opposite to the first surface. The first diffractive structure layer is disposed on the first surface of the substrate. The second diffractive structure layer is disposed on the second surface of the substrate. In the method for fabricating the diffractive optical element, at first, the substrate is provided. Then, a first glue material layer/first semiconductor layer is formed and patterned on the first surface of the substrate. Thereafter, a second glue material layer/second semiconductor layer is formed and patterned on the second surface of the substrate.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventors: Chih-Sheng CHANG, Meng-Ko TSAI, Chung-Kai SHENG
  • Publication number: 20210082839
    Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Publication number: 20210082801
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Chun-Chieh Lu, Chih-Sheng Chang
  • Publication number: 20210074812
    Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh LU, Meng-Hsuan HSIAO, Tung-Ying LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Publication number: 20210075332
    Abstract: A full-bridge resonant conversion circuit comprises a full-bridge rectification unit, a resonant unit, a first transformer, a second transformer and a synchronous rectification unit, wherein the full-bridge rectification unit comprises a first connection end and a second connection end, the resonant unit comprises a first resonant inductor, a resonant capacitor and a second resonant inductor, the resonant capacitor is connected in series with the first resonant inductor or the second resonant inductor. The first transformer comprises a first primary winding connected in series with the first resonant inductor, and a first secondary winding. Also, the second transformer comprises a second primary winding connected in series with the first primary winding and connected with the second resonant inductor, and a second secondary winding connected in parallel with the first secondary winding, and the synchronous rectification unit is connected with the first secondary winding and the second secondary winding.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Inventor: CHIH-SHENG CHANG