Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: The optical component includes a first substrate, a first diffractive layer formed on the first substrate, a second substrate, a second diffractive layer formed on the second substrate, and a bonding material disposed between the first substrate and the second substrate and connecting the first substrate and the second substrate. The second diffractive layer is disposed opposite to the first diffractive layer, and both the first diffractive layer and the second diffractive layer are located between the first substrate and the second substrate. A gap is formed between the first diffractive layer and the second diffractive layer.

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.

Abstract: A semiconductor structure includes a base layer, a metal-containing gate, a high-k layer and a spacer. The metal-containing gate is disposed over the base layer. The high-k layer is disposed between the base layer and the metal-containing gate. The high-k layer has a protruding portion that protrudes out from a bottom of the metal-containing gate. The spacer is disposed on the sidewall of the metal-containing gate and covers the protruding portion of the high-k layer.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

Abstract: The present invention provides an antimicrobial ceramic tile and manufacturing method thereof. A manufacturing method of an antimicrobial ceramic tile comprises: grinding soils into slurries; drying the slurries into powders by hot air; pressing the powders into a green body through a molding machine; dotting or spraying or showering a glaze slurry on the surface of the green body to form an engobe; dotting the glaze slurry on the engobe to form a ground glaze; mixing a surface glaze and an antimicrobial material into an antimicrobial glaze in a weight ratio of 100:5˜10; grinding water and the antimicrobial glaze into the antimicrobial glaze in a weight ratio of 5˜6:4˜5; and dotting antimicrobial glaze on the ground glaze; finally, rapidly firing the ceramic tile and the antimicrobial glaze into an antimicrobial ceramic tile.

Abstract: A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

Abstract: A compound control circuit comprises an input end, a light-load signal processing circuit, a slow response circuit and a fast response circuit. The compound control circuit is mainly used as an additional circuit of a work control chip, so that although the work control chip only has a single overcurrent protection level, a compound function control of fast and slow speed, high and low level current protection and light-load signal stabilization can be generated through the compound control circuit, so as to meet the complex application environment and compatible requirements of the current power supply.

Abstract: A fan driving circuit with temperature compensation comprises a power input end, a power output end connected with a fan motor, a first transistor arranged between the power input end and the power output end, a signal adjuster connected with the first transistor and connected with a signal generating circuit, a second transistor connected with the signal adjuster, and a feedback unit. The feedback unit comprises a first resistor and a second resistor connected in series, and a compensation bypass connected in parallel with the first resistor or the second resistor, wherein the compensation bypass comprises a thermistor, a resistance of the thermistor changes along with the temperature and changes a magnitude of a feedback current which is provided to the second transistor, so as to compensate a change of a common emitter current gain in the second transistor generated by the temperature.

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

Abstract: A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.