Patents by Inventor Chih-Sheng Lin
Chih-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240243124Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.Type: ApplicationFiled: February 15, 2023Publication date: July 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Yang, Shih-Min Lu, Chi-Sheng Tseng, Yao-Jhan Wang, Chun-Hsien Lin
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Patent number: 11969844Abstract: A method for detecting and compensating CNC tools being implemented in an electronic device, receives from a detector first parameters and second parameters in respect of a first tool. Such first parameters include at least one of service life, blade break information, and blade chipping information of the first tool, and such second parameters include at least one of length extension information, length wear information, radial wear information, and blade thickness wear information of the first tool. Based on the first parameters, instructions to process the workpiece are transmitted or not. Upon receiving the second parameters, instructions to adjust operation of the first tool are transmitted, to compensate for deterioration in normal use.Type: GrantFiled: April 12, 2021Date of Patent: April 30, 2024Assignee: Fulian Yuzhan Precision Technology Co., LtdInventors: Hsing-Chih Hsu, Zhao-Yao Yi, Lei Zhu, Chang-Li Zhang, Er-Yang Ma, Chih-Sheng Lin, Feng Xie, Ming-Tao Luo
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Publication number: 20240079051Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.Type: ApplicationFiled: November 8, 2022Publication date: March 7, 2024Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Tuo-Hung Hou, Fu-Cheng Tsai, Jian-Wei Su, Kuo-Hua Tseng
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Patent number: 11741189Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.Type: GrantFiled: January 18, 2023Date of Patent: August 29, 2023Assignee: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20230267973Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.Type: ApplicationFiled: December 5, 2022Publication date: August 24, 2023Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
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Publication number: 20230153375Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Patent number: 11599600Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: GrantFiled: September 6, 2020Date of Patent: March 7, 2023Assignee: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20220413801Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.Type: ApplicationFiled: February 24, 2022Publication date: December 29, 2022Applicant: Industrial Technology Research InstituteInventors: Jian-Wei Su, Chih-Sheng Lin, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Jheng Yang Dai
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Publication number: 20220318605Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.Type: ApplicationFiled: July 26, 2021Publication date: October 6, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Fu-Cheng TSAI, Yi-Ching KUO, Chih-Sheng LIN, Shyh-Shyuan SHEU, Tay-Jyi LIN, Shih-Chieh CHANG
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Patent number: 11423983Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.Type: GrantFiled: May 17, 2021Date of Patent: August 23, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Sheng Lin, Sih-Han Li, Yu-Hui Lin, Jian-Wei Su
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Publication number: 20220223202Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.Type: ApplicationFiled: May 17, 2021Publication date: July 14, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Sheng LIN, Sih-Han LI, Yu-Hui LIN, Jian-Wei SU
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Patent number: 11286453Abstract: Provided is a continuous microalgae culture module, including an outdoor culture unit, a high-density culture unit, a pigment induced unit, and a harvesting unit. A method of culturing microalgae containing macular pigment is also provided, including sequentially culturing microalgae with medium in the outdoor culture unit and the high-density culture unit, producing macular pigment in the pigment induced unit through different light irradiation, and collecting the microalgal biomass containing macular pigment in the harvesting unit.Type: GrantFiled: November 28, 2018Date of Patent: March 29, 2022Assignee: National Chiao Tung UniversityInventors: Chih-Sheng Lin, Chiu-Mei Kuo, Yi-Chun Yang, Wen-Xin Zhang
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Publication number: 20210397675Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.Type: ApplicationFiled: September 6, 2020Publication date: December 23, 2021Applicant: Industrial Technology Research InstituteInventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
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Publication number: 20210316413Abstract: A method for detecting and compensating CNC tools being implemented in an electronic device, receives from a detector first parameters and second parameters in respect of a first tool. Such first parameters include at least one of service life, blade break information, and blade chipping information of the first tool, and such second parameters include at least one of length extension information, length wear information, radial wear information, and blade thickness wear information of the first tool. Based on the first parameters, instructions to process the workpiece are transmitted or not. Upon receiving the second parameters, instructions to adjust operation of the first tool are transmitted, to compensate for deterioration in normal use.Type: ApplicationFiled: April 12, 2021Publication date: October 14, 2021Inventors: HSING-CHIH HSU, ZHAO-YAO YI, LEI ZHU, CHANG-LI ZHANG, ER-YANG MA, CHIH-SHENG LIN, FENG XIE, MING-TAO LUO
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Patent number: 11145356Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: GrantFiled: April 16, 2020Date of Patent: October 12, 2021Assignee: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Publication number: 20210291308Abstract: Provided herein are a numerical control mechanism, a tool replacement equipment and a tool replacement method, which are used for disassembling a first tool and preparing a second tool according to a tool replacement task and replacing the first tool with a second tool, so as to realize automatic tool replacement, reduce manpower and machine waiting time for the tool replacement, and improve the tool replacement efficiency.Type: ApplicationFiled: September 27, 2020Publication date: September 23, 2021Inventors: HSING-CHIH HSU, ZHAO-YAO YI, LEI ZHU, ER-YANG MA, CHIH-SHENG LIN, MING-TAO LUO
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Publication number: 20210257017Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.Type: ApplicationFiled: April 16, 2020Publication date: August 19, 2021Applicant: Industrial Technology Research InstituteInventors: Fu-Cheng Tsai, Heng-Yuan Lee, Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou
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Patent number: 10914618Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.Type: GrantFiled: December 21, 2017Date of Patent: February 9, 2021Assignee: Industrial Technology Research InstituteInventors: Sih-Han Li, Chih-Sheng Lin, Ya-Wen Yang, Kuan-Wei Chen, Shyh-Shyuan Sheu
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Publication number: 20200328142Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.Type: ApplicationFiled: August 12, 2019Publication date: October 15, 2020Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
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Publication number: 20190382704Abstract: Provided is a continuous microalgae culture module, including an outdoor culture unit, a high-density culture unit, a pigment induced unit, and a harvesting unit. A method of culturing microalgae containing macular pigment is also provided, including sequentially culturing microalgae with medium in the outdoor culture unit and the high-density culture unit, producing macular pigment in the pigment induced unit through different light irradiation, and collecting the microalgal biomass containing macular pigment in the harvesting unit.Type: ApplicationFiled: November 28, 2018Publication date: December 19, 2019Inventors: Chih-Sheng Lin, Chiu-Mei Kuo, Yi-Chun Yang, Wen-Xin Zhang