Patents by Inventor Chih-Sheng Lin

Chih-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908749
    Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11876093
    Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Feng Huang, Lung-Sheng Lin
  • Publication number: 20240006304
    Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.
    Type: Application
    Filed: July 4, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Jung-Piao Chiu, Bo-Jiun Lin, Chih-Sheng Chang
  • Publication number: 20230411231
    Abstract: A fan-out type packaging structure includes a strain adjustment layer, a plurality of chips, an encapsulation layer, a redistribution layer, and a plurality of solder balls. The strain adjustment layer is made of a polymer material and has at least 95% laser absorbance. The plurality of chips are partially embedded in the strain adjustment layer and are spaced apart from each other. The encapsulation layer surrounds the chips and is connected to the strain adjustment layer. The redistribution layer covers the encapsulation layer and the chips. The plurality of solder balls are disposed on the redistribution layer and are spaced apart from each other.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Inventors: Chih-Lung YU, Pin-Sheng WANG, Yan-Chiuan LIOU, Yu-Chuan LIU, Yu-Chi LIN, Teng-Kuei CHEN
  • Publication number: 20230386936
    Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Patent number: 11818334
    Abstract: A thermal image-based temperature measurement calibration method applicable to a thermal image device is provided. The method includes a capturing stage, a processing stage and a calibration stage. During the capturing stage, the thermal image device captures a monitored environment to obtain a measured thermal image. During the processing stage, a processor processes on the measured thermal image to obtain a target information, wherein the target information corresponds to a target in the monitored environment, and the target information includes a target image block and a target measured temperature corresponding to the target image block. During the calibration stage, the processor obtains a distance compensation value according to a pixel number of the target image block, and the processor performs a calibration operation to the target measured temperature at least according to the distance compensation value to obtain a calibrated temperature value corresponding to the target.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 14, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng Da Ko, Hung-Sheng Lin, Chun-Te Chuang, Chih-Jen Chen
  • Publication number: 20230363177
    Abstract: Manufacture of a ferroelectric random-access memory device includes forming a first electrode and an intermetal dielectric (IMD) layer over the first electrode. The IMD layer has a first surface on a first side of the IMD layer distal from the first electrode and a second surface on a second side of the IMD layer proximate to the first electrode. A via is created through the IMD layer, which is aligned with the first electrode underneath and has a side wall extending from the first surface of the IMD layer to the second surface of the IMD layer. A ferroelectric layer is deposited over the IMD layer. The ferroelectric layer includes a first part within the via and a second part extending laterally out from the via over the first surface of the IMD layer, the second part thereafter being removed by chemical mechanical polishing.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventors: Yu Chao Lin, Jung-Piao Chiu, Chih-Sheng Chang, Yuan-Tien Tu
  • Patent number: 11809045
    Abstract: Provided is an electronic device including a first liquid crystal layer having a first side and a second side opposite thereto; a second liquid crystal layer disposed on the first liquid crystal layer and having a third side and a fourth side opposite thereto; a first alignment layer disposed on the first side and having a first alignment direction; a second alignment layer disposed on the second side and having a second alignment direction opposite to the first alignment direction; a third alignment layer disposed on the third side and having a third alignment direction; and a fourth alignment layer disposed on the fourth side and having a fourth alignment direction opposite to the third alignment direction. The second alignment layer is between the first liquid crystal layer and the third alignment layer. The third alignment layer is between the second liquid crystal layer and the second alignment layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: November 7, 2023
    Assignee: Innolux Corporation
    Inventors: Chih-Chin Kuo, Mao-Shiang Lin, Yu-Sheng Ho, Ying-Jen Chen, Chih-Yung Hsieh
  • Publication number: 20230352594
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Yen-Sheng LU, Chung-Chi WEN, Yen-Ting CHEN, Wei-Yang LEE, Chia-Pin LIN, Chih-Chiang CHANG, Chien-I KUO, Yuan-Ching PENG, Chih-Ching WANG, Wen-Hsing Hsieh, Chii-Horng LI, Yee-Chia YEO
  • Publication number: 20230343781
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling_Yen YEH, Wilman TSAI, Yee-Chia YEO
  • Publication number: 20230333317
    Abstract: Disclosed is an optical module, including a lower housing, an upper housing covering the lower housing, a circuit board, a first metal base, a second metal base, a silicon photonic chip, and a light emission module including a laser chip and an optical path assembly. The first metal base is disposed on one side of the upper housing. The second metal base is disposed on one side of the lower housing. The circuit board with a hollow region is disposed on the second metal base. The silicon photonic chip is disposed on the second metal base exposed from the hollow region. The laser chip is disposed on the first metal base. The optical path assembly is disposed on the first metal base and/or on the second metal base exposed from the hollow region, and guides a third optical signal emitted by the laser chip to the silicon photonic chip.
    Type: Application
    Filed: December 22, 2022
    Publication date: October 19, 2023
    Applicant: Dongguan Luxshare Technologies Co., Ltd
    Inventors: Chung-Hsin FU, Min-Sheng KAO, ChunFu WU, Yi-Tseng LIN, Chih-Wei YU, Chien-Tzu WU, QianBing YAN, Yueh-Kuo LIN
  • Publication number: 20230334619
    Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Inventors: Chih-Wei Chen, Pei-Kuei Tsung, Yao-Sheng Wang, Chun Chen Lin, Chia-Ching Lin, Hsiao-Chien Chiu
  • Publication number: 20230326882
    Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.
    Type: Application
    Filed: May 2, 2022
    Publication date: October 12, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lung Chou, Ching-Li Yang, Chih-Sheng Chang, Chien-Ting Lin
  • Publication number: 20230328202
    Abstract: A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 12, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yao-Sheng Wang, Pei-Kuei Tsung, Chia-Ni Lu, Yu-Sheng Lin, Chien-Yu Huang, Chih-Wen Goo, Cheng-Lung Jen
  • Patent number: 11783747
    Abstract: A display device includes readout line, first circuit, second circuit, and third circuit. Readout line includes first side and second side. First side is opposite to the second side. Each of first circuit, second circuit, and third circuit is coupled to readout line. Each of first circuit and third circuit is located at first side of readout line. First circuit resets according to first scan signal at first stage. Second circuit is located at second side of readout line. Second circuit and first circuit are arranged in dislocation manner. Second circuit reads first light sensing signal to output to readout line according to first scan signal at first stage. Third circuit and second circuit are arranged in dislocation manner, and third circuit is directly adjacent to first circuit. Third circuit senses light so as to generate second light sensing signal according to second scan signal at first stage.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: October 10, 2023
    Assignee: AUO CORPORATION
    Inventors: Po-Chun Lai, Ling-Ying Chien, Li-Wei Shih, Ching-Sheng Cheng, Chih-Lung Lin, Chia-Lun Lee
  • Publication number: 20230306885
    Abstract: A display device includes readout line, first circuit, second circuit, and third circuit. Readout line includes first side and second side. First side is opposite to the second side. Each of first circuit, second circuit, and third circuit is coupled to readout line. Each of first circuit and third circuit is located at first side of readout line. First circuit resets according to first scan signal at first stage. Second circuit is located at second side of readout line. Second circuit and first circuit are arranged in dislocation manner. Second circuit reads first light sensing signal to output to readout line according to first scan signal at first stage. Third circuit and second circuit are arranged in dislocation manner, and third circuit is directly adjacent to first circuit. Third circuit senses light so as to generate second light sensing signal according to second scan signal at first stage.
    Type: Application
    Filed: December 7, 2022
    Publication date: September 28, 2023
    Inventors: Po-Chun LAI, Ling-Ying CHIEN, Li-Wei SHIH, Ching-Sheng CHENG, Chih-Lung LIN, Chia-Lun LEE
  • Patent number: 11741189
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: August 29, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Patent number: 11740388
    Abstract: The present invention is to provide an anti-glare film. The anti-glare film comprises a polyethylene terephthalate (PET) substrate and an anti-glare layer formed on a surface of the PET substrate, wherein the anti-glare coating layer comprises 75 to 90 weight parts of an acrylic-based resin, 0.01 to 10 weight parts of silica nanoparticles 5 to 20 weight parts of organic microparticles and 0.05 to 2 weight parts of leveling agent. The anti-glare film has a total haze ranging between 35% and 50%, a surface haze ranging between 10% and 15% and a gloss at a viewing angle of 60 degrees between 30% and 50% thereof. The anti-glare film can provide satisfactory anti-glare properties, high precision, surface fineness, no flicker, good visibility and also fine adhesion between layers.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 29, 2023
    Assignee: BenQ Materials Corporation
    Inventors: Tsun Sheng Tao, Chih-Wei Lin, Kuo-Hsuan Yu
  • Publication number: 20230267973
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Application
    Filed: December 5, 2022
    Publication date: August 24, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Patent number: D998758
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 12, 2023
    Inventors: Xiao Hu, Ye-Liang Zhao, Shao-Hui Zhang, Chwung-Shan Kou, Yen-Sheng Wang, Chih-Hung Wang, Chun-Shu Hsu, Szu-Min Lin, Ming-Sheng Tsai, Wen-Wei Gu