Patents by Inventor Chih-Sheng Lin

Chih-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11566775
    Abstract: At least two lighting modules are disposed on a printed circuit board (PCB). Each of the lighting modules includes a plurality of light emitting diode (LED) chips disposed in a non-rectangular array. Lenses are provided over the lighting modules. Each lens has a convex outer surface, and a chamber with a planar or concave inner surface facing a corresponding lighting module and disposed to cover the LED set within the chamber. A light projecting device includes a plurality of LED sets and a plurality of lenses. An orientation part couples each lighting module to the PCB at a non-zero angle.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 31, 2023
    Assignee: TOP VICTORY INVESTMENTS LIMITED
    Inventors: Lieve Lea Andrea Lanoye, Nicolas Philippe Henry Babled, Chih-Feng Lin, Wen-Sheng Lu, Chia-Chih Lin, Dieter Marcel Freddy Verlinde
  • Publication number: 20230020275
    Abstract: The present invention provides a proximity sensing device with linear electrical offset calibration, which can record electrical offsets caused by different dark currents under different settings of the pulse count or the pulse time, and the proximity sensing device uses these electrical offsets to obtain the linear electrical offset ratio. Then calculate and infer the electrical offset generated in actual use through the linear electrical offset ratio to calibrate sensing signal.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 19, 2023
    Inventors: WEN-SHENG LIN, SHENG-CHENG LEE, CHIH-WEI LIN, CHEN-HUA HSI, YUEH-HUNG HOU
  • Patent number: 11557590
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20230004032
    Abstract: Provided is an electronic device including a first liquid crystal layer having a first side and a second side opposite thereto; a second liquid crystal layer disposed on the first liquid crystal layer and having a third side and a fourth side opposite thereto; a first alignment layer disposed on the first side and having a first alignment direction; a second alignment layer disposed on the second side and having a second alignment direction opposite to the first alignment direction; a third alignment layer disposed on the third side and having a third alignment direction; and a fourth alignment layer disposed on the fourth side and having a fourth alignment direction opposite to the third alignment direction. The second alignment layer is between the first liquid crystal layer and the third alignment layer. The third alignment layer is between the second liquid crystal layer and the second alignment layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 5, 2023
    Applicant: Innolux Corporation
    Inventors: Chih-Chin Kuo, Mao-Shiang Lin, Yu-Sheng Ho, Ying-Jen Chen, Chih-Yung Hsieh
  • Publication number: 20220413801
    Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.
    Type: Application
    Filed: February 24, 2022
    Publication date: December 29, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Jian-Wei Su, Chih-Sheng Lin, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Jheng Yang Dai
  • Publication number: 20220406691
    Abstract: An intelligent power module, which includes: a lead frame; a plurality of signal processing chips, disposed on the lead frame; at least one bridge die, configured to operably transmit signals among the signal processing chips; and a package structure, encapsulating the lead frame, the signal processing chips and the bridge die.
    Type: Application
    Filed: December 26, 2021
    Publication date: December 22, 2022
    Inventors: Lung-Sheng Lin, Chih-Feng Huang
  • Publication number: 20220406693
    Abstract: An intelligent power module includes: an encapsulating material structure; a lead frame which is at least partially encapsulated inside the encapsulating material structure, wherein all portions of the lead frame encapsulated inside the encapsulating material structure are at a same planar level; and a heat dissipation structure, which is connected to the lead frame.
    Type: Application
    Filed: May 4, 2022
    Publication date: December 22, 2022
    Inventors: Lung-Sheng Lin, Chih-Feng Huang
  • Patent number: 11532521
    Abstract: A semiconductor structure includes a first fin, which includes a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section, and a second fin, which includes a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section, wherein a shape or an area of the first cross section is different from that of the second cross section.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
  • Publication number: 20220398774
    Abstract: An AI-based object recognition method is provided to recognize an object in a first image captured by a photographic device at a first shooting angle. The method includes: Step A, determining a difference value between the first shooting angle and a preset second shooting angle; Step B, converting the first image into a second image with a view angle of the second shooting angle when the difference value is greater than a preset value; and Step C, sending the second image to an artificial intelligence model for recognition.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 15, 2022
    Inventors: I-Hau YEH, Chia-Hsing LIN, Chih-Sheng Huang, Kuo-Ching HUNG
  • Publication number: 20220386877
    Abstract: The present invention proposes a packaging structure that integrates distance sensing device and temperature sensing device, and it is applied to small wearable devices such as earphones or watches. The combination of distance and temperature sensing allows the wearable device to accurately determine whether it is on the user's body, and then start temperature monitoring. It can collect ear temperature information more effectively and energy-saving.
    Type: Application
    Filed: September 20, 2021
    Publication date: December 8, 2022
    Inventors: WEN-SHENG LIN, SHENG-CHENG LEE, CHIH-WEI LIN, CHEN-HUA HSI, YUEH-HUNG HOU
  • Publication number: 20220384254
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 11513145
    Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Ming-Shiang Lin, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 11508627
    Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11499219
    Abstract: A method of fabricating a thin film with a varying thickness includes the steps of providing a shadow mask with an opening, providing a carrier plate, arranging a substrate on the carrier plate, and coating the substrate through the opening whilst rotating the carrier plate relative to the shadow mask. A plurality of zones of the substrates is swept and exposed from arcuate portions of the opening per each turn by a plurality of predetermined exposure times, respectively. The varying thickness of the thin film corresponds to variation of the predetermined exposure times.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 15, 2022
    Assignee: National Chiao Tung University
    Inventors: Cheng-Sheng Huang, Chi-Yung Hsieh, Yu-Chi Lin, Chih-Chung Wu, Chi-Fang Huang
  • Publication number: 20220358619
    Abstract: A system produces a dolly zoom effect by utilizing side view information. The system first captures a main image at a main location. The main image includes at least a foreground object of a given size and a background. The system calculates one or more side view locations based on a zoom-in factor to be applied to the background and an estimated size of the foreground object. The system then guides a user to capture one or more side view images at the one or more side view locations. The foreground object of the given size is superimposed onto a zoomed-in background. Then the side view information is used by the system to perform image inpainting.
    Type: Application
    Filed: April 18, 2022
    Publication date: November 10, 2022
    Inventors: Chih-Wei Chen, Pei-Kuei Tsung, Yao-Sheng Wang, Chun Chen Lin, Chia-Ching Lin
  • Publication number: 20220359511
    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 11495155
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 8, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Publication number: 20220336612
    Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.
    Type: Application
    Filed: December 10, 2021
    Publication date: October 20, 2022
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG, Chia-Pin LIN, Wei-Yang LEE, Yen-Sheng LU
  • Publication number: 20220328420
    Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Publication number: 20220318605
    Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 6, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fu-Cheng TSAI, Yi-Ching KUO, Chih-Sheng LIN, Shyh-Shyuan SHEU, Tay-Jyi LIN, Shih-Chieh CHANG