Abstract: A laptop computer including a first casing, a first sub-circuit board, an input module, a second casing, a motherboard, and a bridge circuit board is provided. The first sub-circuit board is disposed at the first casing. The input module is disposed at the first casing and electrically connected to the first sub-circuit board. The motherboard is disposed at the second casing. The first casing and the second casing are assembled together, such that the first sub-circuit board, the bridge circuit board, and the motherboard are partially overlapped, and the first sub-circuit board is electrically connected to the motherboard via the bridge circuit board.

Abstract: A laptop computer including a circuit board, a connector, and a fan is provided. The circuit board has a plurality of first electrically conducting members. The connector has a body and a plurality of clamping terminals and pogo pin terminals extended from the body. The clamping terminals and the pogo pin terminals are electrically connected to each other and located at two opposite sides of the body. The clamping terminals clamp the circuit board and are electrically connected to the first electrically conductive members. The fan has a plurality of second electrically conducting members, and the pogo pin terminals are respectively abutted against abutting surfaces of the second electrically conducting members, such that the circuit board is electrically connected to the fan via the connector, wherein each of the abutting surfaces is tilted relative to a plane where the pogo pin terminals are arranged.

Abstract: A laptop computer including a first body, a circuit board disposed in the first body, a second body, a display module disposed in the second body, a hinge connected to the first and the second bodies, and a mezzanine connector is provided. The first and the second bodies are pivoted to each other to be folded or unfolded via the hinge. The mezzanine connector is clamped between the hinge and the circuit board, and is electrically connected between the display module and the circuit board.

Abstract: A laptop computer including a casing, an inner frame, and a plurality of electronic modules is provided. The inner frame is detachably assembled to the casing and forms a plurality of receiving zones separated from each other. The electronic modules are respectively disposed in the receiving zones and connected to each other via a plurality of flexible electrical conducting members, and the electrical conducting members pass through a recess structure of the inner frame.

Abstract: The quality of a frame sequence is enhanced by a booster engine collaborating with a first stage circuit. The first stage circuit adjusts the quality degradation of the frame sequence when a condition in constrained resources is detected. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine receives the frame sequence from the first stage circuit, and generates an enhanced frame sequence based on the frame sequence for transmission to a second stage circuit.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the S/D structure. The bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Abstract: Disclosed is an optical module, including a lower housing, an upper housing covering the lower housing, a circuit board, a first metal base, a second metal base, a silicon photonic chip, and a light emission module including a laser chip and an optical path assembly. The first metal base is disposed on one side of the upper housing. The second metal base is disposed on one side of the lower housing. The circuit board with a hollow region is disposed on the second metal base. The silicon photonic chip is disposed on the second metal base exposed from the hollow region. The laser chip is disposed on the first metal base. The optical path assembly is disposed on the first metal base and/or on the second metal base exposed from the hollow region, and guides a third optical signal emitted by the laser chip to the silicon photonic chip.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: A semiconductor structure includes a base layer, a metal-containing gate, a high-k layer and a spacer. The metal-containing gate is disposed over the base layer. The high-k layer is disposed between the base layer and the metal-containing gate. The high-k layer has a protruding portion that protrudes out from a bottom of the metal-containing gate. The spacer is disposed on the sidewall of the metal-containing gate and covers the protruding portion of the high-k layer.

Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.

Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: A method of forming a semiconductor device is provided. A first ferroelectric inducing layer including Ru is deposited on a substrate. A ferroelectric layer including HfZrO is deposited on the first ferroelectric inducing layer. A second ferroelectric inducing layer including Ru is deposited on the ferroelectric layer, wherein the HfZrO of the ferroelectric layer is in physical contact with the Ru of the first ferroelectric inducing layer and the Ru of the second ferroelectric inducing layer. The second ferroelectric inducing layer, the ferroelectric layer and the first ferroelectric inducing layer are patterned.

Abstract: A system produces a dolly zoom effect by utilizing side view information. The system first captures a main image at a main location. The main image includes at least a foreground object of a given size and a background. The system calculates one or more side view locations based on a zoom-in factor to be applied to the background and an estimated size of the foreground object. The system then guides a user to capture one or more side view images at the one or more side view locations. The foreground object of the given size is superimposed onto a zoomed-in background. Then the side view information is used by the system to perform image inpainting.

Abstract: The present invention discloses a set of novel epigenetic biomarkers for early prediction, treatment response, recurrence and prognosis monitoring of a breast cancer. Aberrant methylation of the genes can be detected in tumor tissues and plasma samples from breast cancer patients but not in normal healthy individual. The present disclosure also discloses primers and probes used herein.

Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.

Abstract: Disclosed are a co-packaged integrated optoelectronic module and a co-packaged optoelectronic switch chip. The co-packaged integrated optoelectronic module includes a carrier board, and an optoelectronic submodule, a slave microprocessor and a master microprocessor disposed on and electrically connected to the carrier board. In the optoelectronic submodule, a digital signal processing chip converts an electrical analog signal into an electrical digital signal, an optoelectronic signal analog conversion chip converts an optical analog signal into the electrical analog signal to the digital signal processing chip, and an optical transceiver chip receives and transmits the optical analog signal to the optoelectronic signal analog conversion chip. The slave microprocessor monitors operation of the optoelectronic submodule.