Patents by Inventor Chih-Sheng Lin

Chih-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368271
    Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 14, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Sih-Han Li, Chih-Sheng Lin
  • Publication number: 20160012958
    Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.
    Type: Application
    Filed: April 22, 2015
    Publication date: January 14, 2016
    Inventors: Sih-Han Li, Chih-Sheng Lin
  • Patent number: 9136843
    Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 15, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Ling Tseng, Keng-Li Su, Chih-Sheng Lin, Shyh-Shyuan Sheu
  • Publication number: 20150214169
    Abstract: A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 ?m, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.
    Type: Application
    Filed: April 10, 2015
    Publication date: July 30, 2015
    Inventors: Chih-Sheng Lin, Chun-Lung Chen, Hsin-Hung Lee
  • Patent number: 9086455
    Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 21, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Chi Lai, Chih-Sheng Lin, Pi-Feng Chiu, Zhe-Hui Lin
  • Patent number: 9076771
    Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: July 7, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Sih-Han Li, Pei-Ling Tseng, Zhe-Hui Lin, Chih-Sheng Lin
  • Patent number: 9064837
    Abstract: A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: June 23, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
  • Publication number: 20140340113
    Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Pei-Ling TSENG, Keng-Li SU, Chih-Sheng LIN, Shyh-Shyuan SHEU
  • Publication number: 20140184346
    Abstract: A voltage-controlled oscillator (VCO) is provided. The VCO includes an oscillator unit disposed on a substrate, and a varactor unit. The varactor unit is coupled to the oscillator unit to form a VCO loop. The varactor unit includes a varactor and at least one control terminal. The varactor is disposed in the substrate, and includes at least two through-silicon via (TSV) structures. The at least one control terminal renders the varactor unit to be biased to change a capacitance value of the varactor.
    Type: Application
    Filed: June 11, 2013
    Publication date: July 3, 2014
    Inventors: Sih-Han LI, Chih-Sheng LIN, Hsin-Chi LAI, Keng-Li SU
  • Publication number: 20140175606
    Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
    Type: Application
    Filed: August 23, 2013
    Publication date: June 26, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sih-Han Li, Pei-Ling Tseng, Zhe-Hui Lin, Chih-Sheng Lin
  • Patent number: 8581419
    Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: November 12, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Keng-Li Su, Hsin-Chi Lai, Chih-Sheng Lin, Zhe-Hui Lin
  • Publication number: 20130236951
    Abstract: The present invention relates to biogas and biogas electric generator and a biogas electricity generation method by use microalgae for removal of carbon dioxide generated from biogas and biogas electric generator. The electric generator integrates biogas production and purification, microalga culture, electricity generation, heat recycling and others into a unit volume, and, during microalgae culturing, uses carbon dioxide contained in biogas and that produced from electricity generation as a carbon source for photosynthesis to reduce the carbon dioxide contained in the biogas and the electricity generation exhaust gas, thereby attaining the goal of zero carbon emission.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 12, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ching-Ping TSENG, Chih-Sheng LIN, Chiun-Hsun CHEN
  • Patent number: 8507909
    Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: August 13, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Ra-Min Tain, Ming-Ji Dai, Shyh-Shyuan Sheu, Chih-Sheng Lin, Shih-Hsien Wu
  • Publication number: 20130093454
    Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 18, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Chi Lai, Chih-Sheng Lin, Pi-Feng Chiu, Zhe-Hui Lin
  • Publication number: 20130059369
    Abstract: A microalgae cultivation module for carbon reduction and biomass production is provided, which includes a first photobioreactor set, a second photobioreactor set, a gas switching device and a control unit. The gas switching device is communicated to the first and the second photobioreactor sets. The control unit is coupled to and controls the gas switching device, thereby aerating a waste gas into the first photobioreactor set and aerating air into the second photobioreactor set for a first predetermined time, then aerating the waste gas into the second photobioreactor set and aerating the air into the first photobioreactor set for a second predetermined time. The first and the second photobioreactor sets include a microalgae species.
    Type: Application
    Filed: January 17, 2012
    Publication date: March 7, 2013
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chih-Sheng Lin, Sheng-Yi Chiu, Chien-Ya Kao
  • Publication number: 20130020952
    Abstract: The present invention is related to AC direct drive organic light emitting diode assembly which comprises parallelly connected a positive duty OLED serial and a negative duty OLED serial receiving an AC voltage. A positive duty of the AC voltage actives the positive serial OLED to generates light output and a negative duty of the AC voltage lights on the negative serial OLED so that the present invention can be driven directly with AC power. The present invention provides a sparkless light output OLED assembly having a very low production cost and being very convenience to use.
    Type: Application
    Filed: July 4, 2012
    Publication date: January 24, 2013
    Inventors: Yu Pin Liao, Chih Sheng Lin
  • Patent number: 8314434
    Abstract: A light emitting diode module includes a substrate, at least two spaced apart light emitting diodes formed on the substrate, an insulating layer, and an electrically conductive layer. Each of the light emitting diodes includes a light emitting unit, an n-electrode, and a p-electrode. The light emitting unit has first and second portions. The first portion has an n-type top face and a first stepped side. The second portion has a p-type top face and a second stepped side. The insulating layer is formed on the n-type top face and the first stepped side of the first portion of one of the light emitting diodes, and the second stepped side and the p-type top face of the second portion of the other one of the light emitting diodes. The electrically conductive layer is formed on the insulating layer. A method of making the light emitting diode module is also disclosed.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: November 20, 2012
    Assignee: Ubilux Optoelectronics Corporation
    Inventors: Chih-Sheng Lin, Shun-Hong Zheng
  • Publication number: 20120249178
    Abstract: A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
  • Patent number: 8236154
    Abstract: The present invention provides a surface-modified electrode strip for measuring an electrochemical signal that is synergistically amplified by means of a nano-scaled gold particle layer and a lipid-soluble electron mediator layer. A biosensor comprising the electrode strip is also provided.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: August 7, 2012
    Assignee: Apex Biotechnology Corp.
    Inventors: Sz-Hau Chen, Chih-Sheng Lin, Guan-Tin Chen, Yueh-Hui Lin, Thomas Y. S. Shen
  • Patent number: 8219340
    Abstract: A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao