Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.

Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract: This invention is an intruder detection system which integrates wireless sensor network and security robots. Multiple ZigBee wireless sensor modules installed in the environment can detect intruders and abnormal conditions with various sensors, and transmit alert to the monitoring center and security robot via the wireless mesh network. The robot can navigate in the environment autonomously and approach to a target place using its localization system. If any possible intruder is detected, the robot can approach to that location, and transmit images to the mobile devices of the securities and users, in order to determine the exact situation in real time.

Abstract: A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.

Abstract: A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part.

Abstract: A light emitting diode module includes a substrate, at least two spaced apart light emitting diodes formed on the substrate, an insulating layer, and an electrically conductive layer. Each of the light emitting diodes includes a light emitting unit, an n-electrode, and a p-electrode. The light emitting unit has first and second portions. The first portion has an n-type top face and a first stepped side. The second portion has a p-type top face and a second stepped side. The insulating layer is formed on the n-type top face and the first stepped side of the first portion of one of the light emitting diodes, and the second stepped side and the p-type top face of the second portion of the other one of the light emitting diodes. The electrically conductive layer is formed on the insulating layer. A method of making the light emitting diode module is also disclosed.

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract: A light-emitting diode device includes: a substrate; a light-emitting layered structure disposed on the substrate and including a first cladding layer, an active layer, and a second cladding layer; a first electrode; a second electrode disposed on the light-emitting layered structure; and a current blocking region provided in the light-emitting layered structure below the second electrode, and having a main portion that is aligned below and is as large as the second electrode, and an extension portion extending from the main portion and protruding beyond the second electrode to a distance ranging from 3 ?m to 20 ?m.

Abstract: A light-emitting diode device includes: a substrate; and a semiconductor layered structure including an n-type semiconductor layer that has an exposed region, and a p-type semiconductor layer that is disposed over the n-type semiconductor layer without extending over the exposed region. An electrode unit is electrically coupled to the semiconductor layered structure, and includes a first electrode and a second electrode. The second electrode has an electrode pad, an end node, and a connecting strip. The electrode pad is larger than the end node. The connecting strip is narrower than the end node.

Abstract: A sensing platform includes: a plurality of metal nanoparticles; a plurality of aggregate inducers each comprising first and second functional groups different from each other, and the first functional group of the aggregate inducers being in contact with the metal nanoparticles; and a plurality of recognition molecules for binding the metal nanoparticles and for interacting with a target to recognize the target, wherein the second functional group of the aggregate inducers is free from being in contact with the metal nanoparticles, and is used to induce the metal nanoparticles to aggregate after the recognition molecules interact with the target.

Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Abstract: A method of making a rough substrate includes: (a) forming a first oxide layer; (b) coating a photoresist layer; (c) exposing and developing the photoresist layer; (d) etching parts of the first oxide layer such that parts of the first oxide layer are formed into a plurality of sacrificial protrusions; (e) removing the photoresist regions; (f) depositing on the substrate layer and the sacrificial protrusions a second oxide layer; (g) etching the second oxide layer so as to leave portions of the second oxide layer; and (h) etching additionally the sacrificial protrusions, the substrate layer, and the portions of the second oxide layer, thereby producing a plurality of flat recess bottom faces, and substrate protrusions.

Abstract: A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part.

Abstract: A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit includes a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N?1 reference signals by detecting the impedance states of a reference circuit having 2N?1 impedance paths; a median signal generating circuit, for generating (2N?1)?1, median signals by receiving the 2N?1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N?1) median signals. The present invention further provides a memory accessing method thereof.

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract: This invention is an intruder detection system which integrates wireless sensor network and security robots. Multiple ZigBee wireless sensor modules installed in the environment can detect intruders and abnormal conditions with various sensors, and transmit alert to the monitoring center and security robot via the wireless mesh network. The robot can navigate in the environment autonomously and approach to a target place using its localization system. If any possible intruder is detected, the robot can approach to that location, and transmit images to the mobile devices of the securities and users, in order to determine the exact situation in real time.

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit comprises a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N?1 reference signals by detecting the impedance states of a reference circuit having 2N?1 impedance paths; a median signal generating circuit, for generating (2N?1)?1, median signals by receiving the 2N?1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N?1) median signals. The present invention further provides a memory accessing method thereof.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.