Patents by Inventor Chih-Tsung Shih

Chih-Tsung Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnection structure and methods of fabrication the same
    Patent number: 10522464
    Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Tsung Shih
  • Methods and apparatus for removing contamination from lithographic tool
    Patent number: 10509334
    Abstract: Embodiments described herein provide a method for cleaning contamination from sensors in a lithography tool without requiring recalibrating the lithography tool. More particularly, embodiments described herein teach cleaning the sensors using hydrogen radicals for a short period while the performance drifting is still above the drift tolerance. After a cleaning process described herein, the lithography tool can resume production without recalibration.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Wen Chen, Po-Chung Cheng, Chih-Tsung Shih, Li-Jui Chen, Shih-Chang Shih
  • LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS
    Publication number: 20190348409
    Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • Layout modification method for exposure manufacturing process
    Patent number: 10366973
    Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • METHOD OF CONTROLLING RETICLE MASKING BLADE POSITIONING TO MINIMIZE IMPACT ON CRITICAL DIMENSION UNIFORMITY AND DEVICE FOR CONTROLLING RETICLE MASKING BLADE POSITIONING
    Publication number: 20190163046
    Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.
    Type: Application
    Filed: October 3, 2018
    Publication date: May 30, 2019
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • METHOD AND APPARATUS FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION
    Publication number: 20190146349
    Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer having a plurality of exposure fields over a wafer stage. The method further includes projecting an extreme ultraviolet (EUV) light over the semiconductor wafer. The method also includes securing the semiconductor wafer to the wafer stage by applying a first adjusted voltage to an electrode of the wafer stage while the EUV light is projected to a first group of the exposure fields of the semiconductor wafer. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.
    Type: Application
    Filed: June 27, 2018
    Publication date: May 16, 2019
    Inventors: Cheng-Kuan WU, Po-Chung CHENG, Li-Jui CHEN, Chih-Tsung SHIH
  • METHOD AND APPARATUS FOR COLLECTING INFORMATION USED IN IMAGE-ERROR COMPENSATION
    Publication number: 20190137866
    Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.
    Type: Application
    Filed: February 27, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS
    Publication number: 20190131290
    Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Hung-Wen CHO, Fu-Jye LIANG, Chun-Kuang CHEN, Chih-Tsung SHIH, Li-Jui CHEN, Po-Chung CHENG, Chin-Hsiang LIN
  • Method for integrated circuit patterning
    Patent number: 10276372
    Abstract: A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • EUV pellicle fabrication methods and structures thereof
    Patent number: 10274819
    Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Jeng-Horng Chen, Chih-Cheng Lin, Hsin-Chang Lee, Shinn-Sheng Yu, Ta-Cheng Lien, Anthony Yen
  • Mask with Multilayer Structure and Manufacturing Method by Using the Same
    Publication number: 20190113835
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • METHODS AND APPARATUS FOR REMOVING CONTAINMINATION FROM LITHOGRAPHIC TOOL
    Publication number: 20190101838
    Abstract: Embodiments described herein provide a method for cleaning contamination from sensors in a lithography tool without requiring recalibrating the lithography tool. More particularly, embodiments described herein teach cleaning the sensors using hydrogen radicals for a short period while the performance drifting is still above the drift tolerance. After a cleaning process described herein, the lithography tool can resume production without recalibration.
    Type: Application
    Filed: February 19, 2018
    Publication date: April 4, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zi-Wen Chen, Po-Chung Cheng, Chih-Tsung Shih, Li-Jui Chen, Shih-Chang Shih
  • RETICLE BACKSIDE INSPECTION METHOD
    Publication number: 20190102875
    Abstract: A method of inspecting a reticle includes obtaining a first image of a surface of the reticle at a first height by scanning the reticle surface with a light source at the first height of the reticle surface relative to a reference surface height of the reticle surface and obtaining a second image of the reticle surface at a second height by scanning the reticle surface with the light source at the second height of the reticle surface relative to the reference surface height of the reticle surface. The second height is different from the first height. The first and the second images are then combined to obtain a surface profile image of the reticle.
    Type: Application
    Filed: August 29, 2018
    Publication date: April 4, 2019
    Inventors: Zi-Wen CHEN, Po-Chung CHENG, Chih-Tsung SHIH, Li-Jui CHEN, Shih-Chang SHIH
  • Mask with multilayer structure and manufacturing method by using the same
    Patent number: 10168611
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • High Durability Extreme Ultraviolet Photomask
    Publication number: 20180373138
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Application
    Filed: August 27, 2018
    Publication date: December 27, 2018
    Inventors: CHIA-HAO YU, CHI-LUN LU, CHIH-TSUNG SHIH, CHING-WEI SHEN, JENG-HORNG CHEN
  • PELLICLE FOR EUV MASK AND FABRICATION THEREOF
    Publication number: 20180341174
    Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 29, 2018
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • EUV LITHOGRAPHY MASK WITH A POROUS REFLECTIVE MULTILAYER STRUCTURE
    Publication number: 20180314144
    Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). The lithography mask also includes a reflective structure disposed over the substrate. The reflective structure includes a first layer and a second layer disposed over the first layer. At least the second layer is porous. The mask is formed by forming a multilayer reflective structure over the LTEM substrate, including forming a plurality of repeating film pairs, where each film pair includes a first layer and a porous second layer. A capping layer is formed over the multilayer reflective structure. An absorber layer is formed over the capping layer.
    Type: Application
    Filed: October 31, 2017
    Publication date: November 1, 2018
    Inventors: Chih-Tsung Shih, Shih-Chang Shih, Li-Jui Chen, Po-Chung Cheng
  • High durability extreme ultraviolet photomask
    Patent number: 10061191
    Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Yu, Chi-Lun Lu, Chih-Tsung Shih, Ching-Wei Shen, Jeng-Horng Chen
  • Pellicle for EUV mask and fabrication thereof
    Patent number: 10031411
    Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 10007174
    Abstract: A mask for extreme ultraviolet lithography (EUVL) is disclosed. The mask includes a low thermal expansion material (LTEM) layer; and a reflective multilayer (ML) above one surface of the LTEM layer, wherein the reflective ML has a first thickness in a first reflective region and a second thickness in a second reflective region, wherein the second thickness is different from the first thickness.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen