Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

Abstract: In accordance with some embodiments, a method for processing a semiconductor wafer is provided. The method includes transporting a carrier along with a reticle supported by the carrier in a lithography exposure apparatus. The method also includes regulating particles in the carrier through a magnetic field. In addition, the method includes removing the reticle from the carrier. The method further includes performing, using the reticle, a lithography exposure process to the semiconductor wafer in the lithography exposure apparatus.

Abstract: A method of inspecting a reticle includes obtaining a first image of a surface of the reticle at a first height by scanning the reticle surface with a light source at the first height of the reticle surface relative to a reference surface height of the reticle surface and obtaining a second image of the reticle surface at a second height by scanning the reticle surface with the light source at the second height of the reticle surface relative to the reference surface height of the reticle surface. The second height is different from the first height. The first and the second images are then combined to obtain a surface profile image of the reticle.

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). The lithography mask also includes a reflective structure disposed over the substrate. The reflective structure includes a first layer and a second layer disposed over the first layer. At least the second layer is porous. The mask is formed by forming a multilayer reflective structure over the LTEM substrate, including forming a plurality of repeating film pairs, where each film pair includes a first layer and a porous second layer. A capping layer is formed over the multilayer reflective structure. An absorber layer is formed over the capping layer.

Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.

Abstract: A lithography apparatus is provided. The lithography apparatus includes a wafer stage configured to secure a semiconductor wafer and having a plurality of electrodes. The lithography apparatus also includes an exposure tool configured to perform an exposure process by projecting an extreme ultraviolet (EUV) light on the semiconductor wafer. The lithography apparatus further includes a controller configured to control power supplied to the electrodes to have a first adjusted voltage during the exposure process for a first group of exposure fields on the semiconductor wafer so as to secure the semiconductor wafer to the wafer stage. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.

Abstract: In accordance with some embodiments, a method for processing a semiconductor wafer is provided. The method includes transporting a carrier along with a reticle supported by the carrier in a lithography exposure apparatus. The method also includes regulating particles in the carrier through a magnetic field. In addition, the method includes removing the reticle from the carrier. The method further includes performing, using the reticle, a lithography exposure process to the semiconductor wafer in the lithography exposure apparatus.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.

Abstract: The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.

Abstract: A method of inspecting a reticle includes obtaining a first image of a surface of the reticle at a first height by scanning the reticle surface with a light source at the first height of the reticle surface relative to a reference surface height of the reticle surface and obtaining a second image of the reticle surface at a second height by scanning the reticle surface with the light source at the second height of the reticle surface relative to the reference surface height of the reticle surface. The second height is different from the first height. The first and the second images are then combined to obtain a surface profile image of the reticle.

Abstract: An extreme ultraviolet (EUV) lithography system includes an extreme ultraviolet (EUV) radiation source to emit EUV radiation, a collector for collecting the EUV radiation and focusing the EUV radiation, a reticle stage for supporting a reticle including a pellicle for exposure to the EUV radiation, and at least one sensor configured to detect particles generated due to breakage of the pellicle.

Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer having a plurality of exposure fields over a wafer stage. The method further includes projecting an extreme ultraviolet (EUV) light over the semiconductor wafer. The method also includes securing the semiconductor wafer to the wafer stage by applying a first adjusted voltage to an electrode of the wafer stage while the EUV light is projected to a first group of the exposure fields of the semiconductor wafer. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.

Abstract: A photomask includes a substrate, a multilayer stack disposed over the substrate and configured to reflect a radiation, a capping layer over the multilayer stack, and an anti-reflective layer over the capping layer. The anti-reflective layer comprises a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced apart from the printable feature from a top-view perspective.

Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.

Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.

Abstract: Embodiments described herein provide a method for cleaning contamination from sensors in a lithography tool without requiring recalibrating the lithography tool. More particularly, embodiments described herein teach cleaning the sensors using hydrogen radicals for a short period while the performance drifting is still above the drift tolerance. After a cleaning process described herein, the lithography tool can resume production without recalibration.

Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.

Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.