Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A heat dissipation device includes a vapor chamber for contacting a heat source; at least one heat pipe having a first end and a second end connected to the vapor chamber; at least one partition disposed inside the heat pipe to partition the inside of the heat pipe into a first channel and a second channel isolated from each other; and a heat dissipation fin set disposed on the vapor chamber and partially covers the heat pipe. The vapor chamber is filled with a liquid working medium that absorbs the heat of the heat source and then gasifies into a gaseous working medium. The gaseous working medium moves into the first channel and the second channel to be condensed by the heat dissipation fin set, so the gaseous working medium is liquefied into the liquid working medium, and then the liquid working medium flows back into the vapor chamber.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A multiple detection system is applied to a vehicle and includes a contact-type detection module adapted to generate a contact-type detection datum, a contactless-type detection module adapted to generate a contactless-type detection datum, and an operation processor electrically connected with the contact-type detection module and the contactless-type detection module in a wire manner or in a wireless manner. The operation processor sets at least one of the contact-type detection datum and the contactless-type detection datum according to an environmental status of the vehicle to be a main detection result of the multiple detection system, and further sets the other detection datum to be an auxiliary detection result of the multiple detection system, for acquiring a passenger feature inside the vehicle.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method and apparatus for video coding are disclosed for the encoder side and the decoder side. According to the method for the decoder side, encoded data associated with a current block is received. A pseudo GPM in a target GPM group for the current block is determined. The current block is divided into one or more subblocks. Assigned MVs (Motion Vectors) of each subblock are determined according to the pseudo GPM. A cost for each GPM in the target GPM group is determined according to decoded data. A selected GPM is determined based on a mode syntax and a reordered target GPM group corresponding to the target GPM group reordered according to the costs, wherein the pseudo GPM is allowed to be different from the selected GPM. The encoded data is decoded using information comprising the selected GPM.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Abstract: A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.

Abstract: An electrostatic discharge protection device includes a P-type substrate, an N-type well, a first P-type heavily-doped area, an N-type doped area, and a first N-type heavily-doped area. The N-type well is formed in the P-type substrate. The first P-type heavily-doped area is formed in the N-type well. The N-type doped area and the first N-type heavily-doped area are formed in the P-type substrate. The N-type doped area is coupled to the N-type well through an external conductive wire decoupled to the first P-type heavily-doped area. Alternatively, the P-type substrate and the N-type well are respectively replaced with an N-type substrate and a P-type well.

Abstract: A method includes receiving a carrier, the carrier including a carrier body, a first filter, and a housing securing the first filter to the carrier body. The method further includes uninstalling the housing from the carrier, replacing the first filter with a second filter, reinstalling the housing on the carrier body, and inspecting the second filter. Inspecting the second filter includes using an automatic inspection mechanism to detect surface flatness of the second filter.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Abstract: An evaporating concave-convex platform structure of a vapor chamber and a manufacturing method thereof, the structure include a lower plate and an upper plate. The lower plate includes a main plate member and a concave-convex member. The main plate member has a chamber portion dented from one surface thereof and a frame edge surrounding a periphery of the chamber portion. The upper plate is stacked on the lower plate facing a dented surface of the chamber portion. The concave-convex member has a concave-convex surface disposed protrusively from the chamber portion of the lower plate or disposed concavely toward the chamber portion. A connecting portion is disposed to surrounds a periphery of the concave-convex surface. The connecting portion is stacked on the main plate member through the concave-convex surface. The connecting portion is welded to the main plate member.