Patents by Inventor Chih-Wei Chen
Chih-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113429Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.Type: ApplicationFiled: August 16, 2023Publication date: April 4, 2024Applicant: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
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Publication number: 20240113113Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Publication number: 20240113061Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.Type: ApplicationFiled: December 5, 2023Publication date: April 4, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
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Patent number: 11947252Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first portion and a matrix structure. The first portion is connected to a first optical member and corresponds to a first light. The matrix structure is disposed on the first portion and corresponds to a second light, wherein the first light is different from the second light. The matrix structure includes a regularly-arranged structure.Type: GrantFiled: December 16, 2022Date of Patent: April 2, 2024Assignee: TDK TAIWAN CORP.Inventors: Chih-Wei Weng, Juei-Hung Tsai, Shu-Shan Chen, Mao-Kuo Hsu, Sin-Jhong Song
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Publication number: 20240104288Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
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Patent number: 11943476Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of one or more transform blocks to generate final transform coefficients, and skip signaling a secondary transform index if a position of a last significant coefficient in each considered transform block is less than or equal to a predefined position; otherwise, the video encoding system signals a secondary transform index according to the transform operation.Type: GrantFiled: April 15, 2020Date of Patent: March 26, 2024Assignee: HFI INNOVATION INC.Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240096701Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.Type: ApplicationFiled: May 17, 2023Publication date: March 21, 2024Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
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Publication number: 20240096867Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
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Publication number: 20240096756Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11936645Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.Type: GrantFiled: June 21, 2021Date of Patent: March 19, 2024Assignee: Kingston Digital, Inc.Inventors: Ben Wei Chen, Chih-Hung Wu
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Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240087951Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
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Patent number: 11930174Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.Type: GrantFiled: December 30, 2019Date of Patent: March 12, 2024Assignee: HFI INNOVATION INC.Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
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Publication number: 20240080490Abstract: A video codec receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video codec signals or parses a first syntax element for a first coding mode in a particular set of two or more coding modes. Each of coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate. The video codec enables the first coding mode and disables one or more other coding modes in the particular set of coding modes. The disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes. The video codec encodes or decodes the current block by using the enabled first coding mode and bypassing the disabled coding modes.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicant: HFI Innovation Inc.Inventors: Man-Shu Chiang, Chih-Wei Hsu, Ching-Yeh Chen
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Patent number: 11921307Abstract: The present disclosure provides an optical element driving mechanism, which includes a movable part, a fixed assembly, and a driving assembly. The movable part is configured to be connected to an optical element. The movable part is movable relative to the fixed assembly. The driving assembly is configured to drive the movable part to move relative to the fixed assembly. The movable part includes a connecting assembly configured to position the optical element.Type: GrantFiled: January 7, 2022Date of Patent: March 5, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Hsi Wang, Chao-Chang Hu, Chih-Wei Weng, Kuen-Wang Tsai, Tzu-Ying Chen
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Patent number: 11924444Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.Type: GrantFiled: April 11, 2022Date of Patent: March 5, 2024Assignee: HFI INNOVATION INC.Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: D1018537Type: GrantFiled: November 7, 2023Date of Patent: March 19, 2024Assignee: HTC CORPORATIONInventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen