Abstract: A mouse device includes a multi-touch region on a button. The mouse device includes a touchpad, a press switch, a button cover and a control board. The touchpad triggers a corresponding touch signal when any one of a plurality of touch regions respectively corresponding to a plurality of input events is pressed. A switch signal is triggered when the press switch is pressed. The button cover is used to accept a pressing operation of pressing toward an inner side to press the touchpad, and to press the press switch through the touchpad. When receiving the touch signal and the switch signal, the control board triggers the input event of the pressed touch region.

Abstract: Embodiments provide a mouse device that includes with a plurality of touch areas on one or more mouse buttons. The mouse device includes a touch panel, a press switch, a button cover and a control panel. The touch panel triggers a corresponding touch signal when any one of the plurality of touch areas respectively corresponding to a plurality of input events is pressed. A switch signal is triggered when the press switch is pressed. The button cover is used to receive a pressing operation of pressing, toward inside, the touch panel, and press the press switch via the touch panel. When receiving the touch signal and the switch signal, the control panel triggers the input event of the pressed touch area.

Abstract: The present invention provides a mouse device with a detection function of non-human mouse events and a detection method thereof. A driver receives a plurality of movement mouse events through a computer device from a mouse device, executes a non-human movement detection on the movement mouse events to determine each movement mouse event as a suspicious event or a human-made event, executes an interference process when the suspicious events meet a non-human critical condition, and executes the plurality of movement mouse events when the suspicious events do not meet the non-human critical condition. The present invention can effectively detect non-human movement mouse events, and execute interference on the non-human movement mouse events to deter non-human operations.

Abstract: A mouse device includes a detection function to detect non-human mouse events through encryption and a detection method thereof. A mouse retrieves variable characters, executes an encryption process on a plaintext mouse event to obtain a ciphertext mouse event based on the variable characters and fixed characters. A computer device executes a decryption process on the ciphertext mouse event to obtain the plaintext mouse event when receiving the ciphertext mouse event, executes the plaintext mouse event, and executes an interfering process when the mouse event is different or cannot be decrypted.

Abstract: A wireless keyboard, comprising a body, several keys, a first detection unit, a second detection unit and a control unit. The several keys are disposed on the body. The first detection unit is disposed on one side of the body. The second detection unit is disposed on the other side of the body corresponding to the first detection unit. The first detection unit and the second detection unit jointly detect a feedback signal therebetween. When the feedback signal corresponds to an activation signal, the control unit activates the wireless keyboard. In some implementations, the wireless keyboard can save power, and does not require users to switch on/off the power supply manually, thereby achieving the purpose of facilitating life.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a first source/drain region, a semiconductor layer, a first floating gate electrode, a first control gate electrode, a second floating gate electrode, a second control gate electrode, and an erase gate electrode. The semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode laterally surrounds the first semiconductor layer. The first control gate electrode laterally surrounds the first floating gate electrode and the first semiconductor layer. The second floating gate electrode laterally surrounds the first semiconductor layer. The second control gate electrode laterally surrounds the second floating gate electrode and the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.

Abstract: A method of manufacturing an integrated circuit includes following operations. A stack of a plurality pair of first layers and second layers alternately arranged is formed over a substrate. A plurality of first holes is formed in the stack. An isolation layer is formed to cover sidewalls of the first holes. A plurality of conductive features is formed in the first holes. A plurality of second holes are formed in the stack. Each of the second holes exposes a portion of a sidewall of at least one of the conductive features. A channel layer is formed to cover sidewalls of the second holes and the portions of the sidewalls of the conductive features. The second layers of the stack are replaced with a plurality of gate layers.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

Abstract: A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Abstract: An anti-fuse memory cell includes a substrate, a gate dielectric layer over the substrate, a word line gate over the gate dielectric layer, a first implant region on a first side of the word line gate, a bit line contact plug over the first implant region, a second implant region on a second side of the word line gate opposite the first side of the word line gate, an oxidized region on the second implant region and having a convex upper surface and a source line gate over the convex upper surface of the oxidized region.

Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.