Patents by Inventor Chih-Wei Hung
Chih-Wei Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527630Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.Type: GrantFiled: June 24, 2020Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Pin Chang, Chien-Hung Liu, Chih-Wei Hung
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Publication number: 20220367611Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Fu LIN, Tsung-Hao Yeh, Chih-Wei HUNG
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Publication number: 20220293723Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Fu LIN, Tsung-Hao YEH, Chien-Hung LIU, Shiang-Hung HUANG, Chih-Wei HUNG, Tung-Yang LIN, Ruey-Hsin LIU, Chih-Chang CHENG
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Publication number: 20220284969Abstract: A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Pin CHANG, Chien-Hung LIU, Chih-Wei HUNG
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Publication number: 20210408253Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a first dielectric layer over a substrate; depositing a sacrificial layer over the first dielectric layer; depositing a second dielectric layer over the sacrificial layer; depositing an erase gate electrode layer over the second dielectric layer; etching a memory hole in the erase gate electrode layer, the sacrificial layer, and the first and second dielectric layers; and forming a semiconductor layer in the memory hole.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Pin CHANG, Chien-Hung LIU, Chih-Wei HUNG
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Patent number: 11146717Abstract: A camera module for an imaging device includes a light sensing module, a control circuit, a mounting member, one or more external lens modules, and a magnetic sensing element. The control circuit sets photographic conditions for a certain external lens module according to a control signal, the control signal being prompted by the magnetic sensing element detecting the type of the external lens module by the arrangement of magnetic components therein, as detected by the magnetic sensing element. The magnetic components have configurations corresponding to the type of the external lens module and the magnetic components assist in aligning one external lens module to the body of the imaging device. The automatic detection and photographic settings applied can be disabled by a user.Type: GrantFiled: June 1, 2020Date of Patent: October 12, 2021Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.Inventor: Chih-Wei Hung
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Publication number: 20210288059Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.Type: ApplicationFiled: June 2, 2021Publication date: September 16, 2021Inventors: Chien Hung Liu, Chih-Wei Hung
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Patent number: 11037949Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.Type: GrantFiled: September 4, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien Hung Liu, Chih-Wei Hung
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Patent number: 10879256Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.Type: GrantFiled: June 22, 2018Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien Hung Liu, Chih-Wei Hung
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Patent number: 10878915Abstract: A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.Type: GrantFiled: December 19, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Pin Chang, Hsien-Jung Chen, Chien-Hung Liu, Chih-Wei Hung
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Publication number: 20200296264Abstract: A camera module for an imaging device includes a light sensing module, a control circuit, a mounting member, one or more external lens modules, and a magnetic sensing element. The control circuit sets photographic conditions for a certain external lens module according to a control signal, the control signal being prompted by the magnetic sensing element detecting the type of the external lens module by the arrangement of magnetic components therein, as detected by the magnetic sensing element. The magnetic components have configurations corresponding to the type of the external lens module and the magnetic components assist in aligning one external lens module to the body of the imaging device. The automatic detection and photographic settings applied can be disabled by a user.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventor: CHIH-WEI HUNG
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Patent number: 10715706Abstract: A camera module for an imaging device includes a light sensing module, a control circuit, a mounting member, one or more external lens modules, and a magnetic sensing element. The control circuit sets photographic conditions for a certain external lens module according to a control signal, the control signal being prompted by the magnetic sensing element detecting the type of the external lens module by the arrangement of magnetic components therein, as detected by the magnetic sensing element. The magnetic components have configurations corresponding to the type of the external lens module and the magnetic components assist in aligning one external lens module to the body of the imaging device. The automatic detection and photographic settings applied can be disabled by a user.Type: GrantFiled: November 23, 2018Date of Patent: July 14, 2020Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.Inventor: Chih-Wei Hung
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Publication number: 20200169651Abstract: A camera module for an imaging device includes a light sensing module, a control circuit, a mounting member, one or more external lens modules, and a magnetic sensing element. The control circuit sets photographic conditions for a certain external lens module according to a control signal, the control signal being prompted by the magnetic sensing element detecting the type of the external lens module by the arrangement of magnetic components therein, as detected by the magnetic sensing element. The magnetic components have configurations corresponding to the type of the external lens module and the magnetic components assist in aligning one external lens module to the body of the imaging device. The automatic detection and photographic settings applied can be disabled by a user.Type: ApplicationFiled: November 23, 2018Publication date: May 28, 2020Inventor: CHIH-WEI HUNG
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Publication number: 20200006369Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.Type: ApplicationFiled: September 4, 2019Publication date: January 2, 2020Inventors: Chien Hung Liu, Chih-Wei Hung
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Publication number: 20190157285Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.Type: ApplicationFiled: June 22, 2018Publication date: May 23, 2019Inventors: Chien Hung Liu, Chih-Wei Hung
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Patent number: 9377154Abstract: A bracket for supporting a portable electronic device is disclosed. The bracket includes a base, a housing receiving the portable electronic device and an arm connecting the base with the housing. The arm defines a slot which has a plurality of teeth arranged along a lengthwise direction thereof. A connector extends through the slot of the arm into the housing. The connector has two elastic tabs movably engaging with the teeth to thereby position the housing at different heights of the arm.Type: GrantFiled: November 20, 2013Date of Patent: June 28, 2016Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chih-Wei Hung, Yi-Heng Hsu
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Publication number: 20150076308Abstract: A bracket for supporting a portable electronic device is disclosed. The bracket includes a base, a housing receiving the portable electronic device and an arm connecting the base with the housing. The arm defines a slot which has a plurality of teeth arranged along a lengthwise direction thereof. A connector extends through the slot of the arm into the housing. The connector has two elastic tabs movably engaging with the teeth to thereby position the housing at different heights of the arm.Type: ApplicationFiled: November 20, 2013Publication date: March 19, 2015Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHIH-WEI HUNG, YI-HENG HSU
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Patent number: 8300462Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.Type: GrantFiled: February 6, 2012Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
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Patent number: 8243527Abstract: A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.Type: GrantFiled: August 15, 2011Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Hung, Chia-Ta Hsieh, Luan C. Tran
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Publication number: 20120134209Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen