Patents by Inventor Chih-Wei Lee

Chih-Wei Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111029
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: November 30, 2020
    Publication date: April 15, 2021
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 10978261
    Abstract: A method for fabricating a keyboard covering film is provided. The method includes steps of: coating a transparent plastic material on an upper surface of a fabric layer before the transparent plastic material is cured; treating the fabric layer and the transparent plastic material by a hot press process to cure the transparent plastic material to form a transparent layer and to make the transparent layer and the fabric layer jointly form a number of keycap receiving sections; forming a mask layer on a lower surface of the fabric layer; removing a portion of the mask layer and a portion of the fabric layer located within each of the keycap receiving sections to form a number of hollow patterns.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 13, 2021
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Zheng-Hong Lai, Chih-Ho Hsu, Che-Wei Lee, Jin-Long Chan, Yuan-bao Chen, Chang-En Sun
  • Patent number: 10964888
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ren Dai, Chung-Ju Lee, Chung-Te Lin, Chih-Wei Lu, Hsi-Wen Tien, Tai-Yen Peng, Chien-Min Lee, Wei-Hao Liao
  • Publication number: 20210082804
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20210074011
    Abstract: A tooth-position recognition system includes an electronic device and a calculation device. The electronic device includes a first camera. The first camera is configured to capture a plurality of tooth images. The calculation device includes a second camera and a processor. The second camera is configured to capture a user image. The processor is configured to receive the tooth images, compare the corresponding position of each pixel in each tooth image to generate a depth map, and input the tooth images, the depth map, and a plurality of first tooth-region identifiers into a tooth deep-learning model. The tooth deep-learning model outputs a plurality of deep-learning probability values that are the same in number as the first tooth-region identifiers. The processor inputs the user image and the plurality of second tooth-region identifiers into a user-image deep-learning model.
    Type: Application
    Filed: December 9, 2019
    Publication date: March 11, 2021
    Inventors: Kai-Ju CHENG, Kuan-Chung CHEN, Yu-Cheng CHIEN, Chung-Sheng WU, Hao-Ping LEE, Chin-Yuan TING, Yu-Hsun CHEN, Shao-Ang CHEN, Jia-Chyi WANG, Chih-Wei SUNG
  • Patent number: 10944005
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Publication number: 20210066490
    Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Inventors: Chansyun David Yang, Han-Yu Lin, Chun-Yu Chen, Chih-Ching Wang, Fang-Wei Lee, Tze-Chung LIN, Li-Te LIN, Gwan-Sin Chang, Pinyen LIN
  • Publication number: 20210061643
    Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
  • Publication number: 20210043569
    Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10917418
    Abstract: A data packet is received. The data packet is a unit of data transmitted across a packet-switched network. A determination is made whether a new connection is detected. The data packet is transmitted using the new connection. In response to determining that a new connection is detected, a connection context for the new connection is added to a current connection context in a dynamic event table. The dynamic event table includes the current connection context, one or more previous connection contexts, and a listing of one or more events. Each event of the one or more events is a malicious activity and is retrieved from a repository. A score for each event is calculated based on the current connection context. Each event in the dynamic event table is prioritized based on the calculated score for each event. The event with the highest score receives the highest priority.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Wen Chao, Hsin-Yu Chuang, Ming-Pin Hsueh, Sheng-Wei Lee
  • Publication number: 20210036593
    Abstract: A driving mechanism is provided, including a fixed portion, a movable portion, a driving assembly and a connecting element. The movable portion may move relative to the fixed portion and is used for holding an optical module. The driving assembly moves the movable portion relative to the fixed portion. The connecting element is movably connected to the fixed portion and the movable portion.
    Type: Application
    Filed: June 4, 2020
    Publication date: February 4, 2021
    Inventors: Chao-Chang HU, Chen-Hsien FAN, Yueh-Lin LEE, Yu-Chiao LO, Chih-Wei WENG
  • Patent number: 10909431
    Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 2, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chien-Hung Lin, Yu-Sheng Lee, Yung-Chao Chen, Chih-Wei Hsu
  • Publication number: 20210029838
    Abstract: A display, including a carrying main body, a flexible carrier film, a double-sided tape, and an adhesive layer, is provided. The flexible carrier film includes a first bonding section and a second bonding section respectively disposed on two opposite sides of the carrying main body, and a bending section connected between the first bonding section and the second bonding section. The flexible carrier film has an inner surface and an outer surface opposite to each other. The inner surface has at least one first groove at the bending section. The flexible carrier film has a display layer thereon. At least a part of the display layer is connected to the outer surface at the second bonding section. The double-sided tape is disposed between the first bonding section and the carrying main body. The adhesive layer is disposed between the inner surface and the carrying main body at the bending section.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 28, 2021
    Applicant: Au Optronics Corporation
    Inventors: Chih-Tsung Lee, Chih-Chieh Lin, Yi-Wei Tsai, Ko-Chin Chung
  • Publication number: 20210010901
    Abstract: An automatic mounting and demounting device and system for a motor testing platform, adapted to enable a control host to control automatic mounting and demounting between an axle of a motor under test and an axle of a testing apparatus, includes a mobile platform and a positional information sensing member. The control host controls the mobile platform according to positional information generated by the positional information sensing member, such that a carrier for carrying the motor under test is automatically driven to a corresponding position to thereby effect alignment and connection or separation of the axle of the motor under test and the axle of the testing apparatus. Therefore, preparation for the motor dynamics testing is automatically carried out effectively and correctly, thereby reducing the time and manpower required for testing-related preparation.
    Type: Application
    Filed: June 18, 2020
    Publication date: January 14, 2021
    Inventors: MING-YEN CHEN, JIAN-LIN LEE, SHENG-WEI LIN, CHIH-HSIEN WANG
  • Publication number: 20210003136
    Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes an axial induced coil unit and a circuit board. The axial induced coil unit is made by twining a coil in an axial direction for at least two layers and in a radial direction for at least two layers.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Chao-Wen LU, Chih-Wei CHAN, Che-Wei LEE
  • Patent number: 10870576
    Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area; further includes a sensing electrode, a second TiO2-patterned portion, and a second Pt-patterned portion on the second TiO2-patterned portion in the sensing area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, a TiO2 layer formed on the IMD layer, a first TiO2-patterned portion and a first Pt-patterned portion.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
  • Publication number: 20200388616
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10854458
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Patent number: 10818600
    Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao