Abstract: Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers. A wafer bonding system includes a camera configured to monitor bonding between two semiconductor wafers. Wafer bonding defect detection circuitry receives video data from the camera, and detects a bonding defect based on the received video data.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

Abstract: A method for manufacturing a play-of-color article includes the steps of: (a) providing a first mixture that contains a solvent and a plurality of functionalized colloidal particles; (b) replacing the solvent of the first mixture with a polymer solution that contains polymers, thereby obtaining a second mixture; (c) adding an initiator to the second mixture to obtain a third mixture, followed by injecting the third mixture into a mold and disturbing the third mixture, so that the third mixture is formed with a pattern; (d) leaving the third mixture to stand, so as to allow the functionalized colloidal particles therein to self-assemble to form a crystalline arrangement, thereby obtaining a fourth mixture; and (e) subjecting the polymers in the fourth mixture to a cross-linking reaction, thereby obtaining the play-of-color article. A play-of-color article manufactured by the method, and a play-of-color product including the play-of-color article are also provided.

Abstract: A method for storage and supply of a F3NO-free FNO-containing gas comprises the steps of storing the F3NO-free FNO-containing gas in a NiP coated steel cylinder with a polished inner surface, releasing the F3NO-free FNO-containing gas from the cylinder to a manifold assembly by activating a cylinder valve in fluid communication with the cylinder and the manifold assembly, de-pressurizing the F3NO-free FNO-containing gas by activating a pressure regulator in the manifold assembly so as to divide the manifold assembly into a first pressure zone upstream of the pressure regulator and a second pressure zone downstream of the pressure regulator, and feeding the de-pressurized F3NO-free FNO-containing gas to a target reactor downstream of the second pressure zone.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; a support module disposed between the back plate and the optical film; and an adhesive layer disposed between the back plate and the support module, wherein the support module includes a base and a support unit between the base and the optical film, and the base is fixed to the back plate by the adhesive layer.

Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.

Abstract: An electronic device includes a radiator, a first feed circuit, and a second feed circuit. The radiator includes a first branch. The first feed circuit feeds the radiator at a first end of the first branch, and the second feed circuit feeds the radiator at a first position in the first branch. The first position is in an area with a largest current in the first branch when the first feed circuit performs feeding and the second feed circuit does not perform feeding.

Abstract: Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers. A wafer bonding system includes a camera configured to monitor bonding between two semiconductor wafers. Wafer bonding defect detection circuitry receives video data from the camera, and detects a bonding defect based on the received video data.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: An calibration kit includes a base, a combination of calibration parts, and a manipulation part. The combination of calibration parts is disposed on the base and includes a first calibration part and a second calibration part. The first calibration part has a first calibration surface. The second calibration part has a second calibration surface. The first calibration part and the second calibration part are relatively movable in a movement direction and are movable relative to the base. The manipulation part is movably or rotatably disposed on the base. The manipulation part is configured to be operable to drive the first calibration part and the second calibration part to move in the movement direction relative to the base, so that the combination of calibration parts forms a three-dimensional calibration surface configuration through the first calibration surface and the second calibration surface.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; and a support module disposed between the back plate and the optical film, wherein the support module comprises a base and a support unit between the base and the optical film, the base comprises a curved surface away from the back plate, the support unit is connected to an upper surface of the base, and the upper surface comprises the curved surface; wherein a hollow space is enclosed by the base.

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.