Patents by Inventor Chih-Yu Hsu
Chih-Yu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367728Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Publication number: 20220359296Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 11450661Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.Type: GrantFiled: April 20, 2018Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
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Publication number: 20220285161Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.Type: ApplicationFiled: May 20, 2022Publication date: September 8, 2022Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
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Patent number: 11437280Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: June 12, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Publication number: 20220246433Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
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Publication number: 20220208517Abstract: A method for storage and supply of a F3NO-free FNO-containing gas comprises the steps of storing the F3NO-free FNO-containing gas in a NiP coated steel cylinder with a polished inner surface, releasing the F3NO-free FNO-containing gas from the cylinder to a manifold assembly by activating a cylinder valve in fluid communication with the cylinder and the manifold assembly, de-pressurizing the F3NO-free FNO-containing gas by activating a pressure regulator in the manifold assembly so as to divide the manifold assembly into a first pressure zone upstream of the pressure regulator and a second pressure zone downstream of the pressure regulator, and feeding the de-pressurized F3NO-free FNO-containing gas to a target reactor downstream of the second pressure zone.Type: ApplicationFiled: January 13, 2022Publication date: June 30, 2022Inventors: Ayaka NISHIYAMA, Jiro YOKOTA, Chih-yu HSU, Peng SHEN, Nathan STAFFORD
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Patent number: 11342188Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.Type: GrantFiled: September 17, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
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Publication number: 20220102221Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Cheng Hong Yang, Shih-Hao Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11281516Abstract: An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.Type: GrantFiled: December 12, 2019Date of Patent: March 22, 2022Assignee: Realtek Semiconductor Corp.Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Ting Chien, Wei-Hung Chuang, Chih-Yu Hsu
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Publication number: 20210391219Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Publication number: 20210305258Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: ApplicationFiled: September 29, 2020Publication date: September 30, 2021Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11126233Abstract: A circuit includes: a first interface circuit supporting multiple first interface operating modes respectively corresponding to different versions of a first data transmission protocol; a second interface circuit supporting multiple second interface operating modes respectively corresponding to different versions of a second data transmission protocol; a control circuit configured to operably instruct the first interface circuit to operate in a first target operating mode selected from the multiple first interface operating modes, and configured to operably instruct the second interface circuit to operate in a second target operating mode selected from the multiple second interface operating modes; wherein a difference between a nominal data rate of the first target operating mode and a nominal data rate of the second target operating mode is less than a predetermined threshold.Type: GrantFiled: July 15, 2020Date of Patent: September 21, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Yi Ting Chien, Cheng Yuan Hsiao, Chih Yu Hsu, Sung Kao Liu, Wei Hung Chuang
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Patent number: 11024513Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers f using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N@C—)—(R)—(—C?N); Rx[-C?N(Rz)]y; and R(3-a)-N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.Type: GrantFiled: December 29, 2017Date of Patent: June 1, 2021Assignee: Air Liquide Electronics U.S. LPInventors: Chih-Yu Hsu, Peng Shen, Nathan Stafford
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Publication number: 20210082706Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Kuo-Feng Yu, Chun Hsiung Tsai, Jian-Hao Chen, Hoong Shing Wong, Chih-Yu Hsu
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Publication number: 20210048859Abstract: A circuit includes: a first interface circuit supporting multiple first interface operating modes respectively corresponding to different versions of a first data transmission protocol; a second interface circuit supporting multiple second interface operating modes respectively corresponding to different versions of a second data transmission protocol; a control circuit configured to operably instruct the first interface circuit to operate in a first target operating mode selected from the multiple first interface operating modes, and configured to operably instruct the second interface circuit to operate in a second target operating mode selected from the multiple second interface operating modes; wherein a difference between a nominal data rate of the first target operating mode and a nominal data rate of the second target operating mode is less than a predetermined threshold.Type: ApplicationFiled: July 15, 2020Publication date: February 18, 2021Inventors: Yi Ting CHIEN, Cheng Yuan HSIAO, Chih Yu HSU, Sung Kao LIU, Wei Hung CHUANG
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Publication number: 20200379833Abstract: An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.Type: ApplicationFiled: December 12, 2019Publication date: December 3, 2020Inventors: Cheng-Yuan Hsiao, Sung-Kao Liu, Yi-Ting Chien, Wei-Hung Chuang, Chih-Yu Hsu
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Patent number: 10751152Abstract: In this invention, a high-accuracy jaw motion tracking system and method using the same are disclosed. The jaw motion tracking system of the invention mainly comprises an eyewear facebow static positioning device, a lower jaw dynamic tracking device and a stereo-vision charge-coupled device (CCD) and can provide information regarding the locations and relative movement of lower and upper jaws. The eyewear facebow static positioning device has several passive and active reflective markers. The lower jaw dynamic tracking device equips with a plural of lightweight light emitting devices. Using OpenCV-based self-developed algorithm and post-iterative compensator, the disclosed system can record the dynamical jaw movement with a high accuracy. The disclosed jaw motion tracking system and related method have minimal occlusal disturbance and provide smooth motion-tracking performance. The disclosed system can be used in clinical dentistry.Type: GrantFiled: December 21, 2016Date of Patent: August 25, 2020Assignee: NATIONAL YANG-MING UNIVERSITYInventors: Liang-Yuan Cheng, Chih-Yu Hsu, Shyh-Yuan Lee, Yuan-Min Lin
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Publication number: 20200203127Abstract: Disclosed are systems and methods for supplying a F3NO-free FNO-containing gas and systems and methods for etching using the F3NO-free FNO-containing gas. The system comprises a NiP coated steel cylinder with a polished inner surface to store the F3NO-free FNO-containing gas, a cylinder valve to release the F3NO-free FNO-containing gas from the cylinder, a manifold assembly, including a pressure regulator and line components to deliver the F3NO-free FNO-containing gas to a target reactor. The pressure regulator de-pressurizes the F3NO-free FNO-containing gas in the manifold assembly thereby dividing the manifold assembly into a first pressure zone upstream of the pressure regulator and a second pressure zone downstream of the pressure regulator. A gaseous composition comprises F3NO-free FNO gas containing less than approximately 1% F3NO impurity by volume and an inert gas being capable of suppressing the concentration of F3NO impurity in the F3NO-free FNO gas.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Ayaka NISHIYAMA, Jiro Yokota, Chih-yu Hsu, Peng Shen, Nathan Stafford
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Patent number: 10684668Abstract: A USB interface system capable of automatically adjusting connection speed and power consumption capability and a method thereof are provided. The method includes configuring a slave device to perform a first handshake procedure with a main device, and communicate with the main device by using a first connection specification; detecting a first power-off event by using a slave power detection module; when the first power-off event occurs, recording first power-off information by the memory unit. If the slave device is re-connected to the main device, the slave power detection module is configured to perform a second handshake process with the main device, and determine to re-communicate with the main device in a second connection specification different from the first connection specification according to the first power-off information.Type: GrantFiled: July 1, 2019Date of Patent: June 16, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Yi-Ting Chien, Sung-Kao Liu, Cheng-Yuan Hsiao, Wei-Hung Chuang, Chih-Yu Hsu