Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.

Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers f using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N@C—)—(R)—(—C?N); Rx[-C?N(Rz)]y; and R(3-a)-N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.

Abstract: A rhythm fitness step apparatus includes a body and two leg bases. The body has an upper surface and a lower surface, wherein the upper surface is installed with a platform thereon; both sides of the lower surface are formed with an installation space separately. The installation space has a plurality of slots and a plurality of dodge slots concavely and alternately installed therein, wherein the concave depth of the slot and the concave depth of the dodge slot are different so that the depth of the dodge slot is greater than the depth of the slot in design. The leg base has a plate body. The lower surface of the plate body is installed with a cushion pad; the upper surface of the plate body has a plurality of first supporting blocks and a plurality of second supporting blocks protruding therefrom alternately and corresponding to the configuration layout of the slots and the dodge slots of the body.

Abstract: A rhythm fitness step apparatus includes a body and two leg bases. The body has an upper surface and a lower surface, wherein the upper surface is installed with a platform thereon; both sides of the lower surface are formed with an installation space separately. The installation space has a plurality of slots and a plurality of dodge slots concavely and alternately installed therein, wherein the concave depth of the slot and the concave depth of the dodge slot are different so that the depth of the dodge slot is greater than the depth of the slot in design. The leg base has a plate body. The lower surface of the plate body is installed with a cushion pad; the upper surface of the plate body has a plurality of first supporting blocks and a plurality of second supporting blocks protruding therefrom alternately and corresponding to the configuration layout of the slots and the dodge slots of the body.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: In this invention, a high-accuracy jaw motion tracking system and method using the same are disclosed. The jaw motion tracking system of the invention mainly comprises an eyewear facebow static positioning device, a lower jaw dynamic tracking device and a stereo-vision charge-coupled device (CCD) and can provide information regarding the locations and relative movement of lower and upper jaws. The eyewear facebow static positioning device has several passive and active reflective markers. The lower jaw dynamic tracking device equips with a plural of lightweight light emitting devices. Using OpenCV-based self-developed algorithm and post-iterative compensator, the disclosed system can record the dynamical jaw movement with a high accuracy. The disclosed jaw motion tracking system and related method have minimal occlusal disturbance and provide smooth motion-tracking performance. The disclosed system can be used in clinical dentistry.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: An image signal processing method includes: receiving an original color filter array (CFA) image and a pixel binned CFA image; computing a specific information of the pixel binned CFA image; and processing the original CFA image according to the specific information. The associated image signal processor includes an input terminal, an operating unit and a processing unit, wherein the input terminal is for receiving an original CFA image and a pixel binned CFA image, the operating unit is for computing a specific information of the pixel binned CFA image, and the processing unit is for processing the original CFA image according to the specific information and utilizing the pixel binned CFA image.

Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin.

Abstract: An image signal processing method includes: receiving an original color filter array (CFA) image and a pixel binned CFA image; computing a specific information of the pixel binned CFA image; and processing the original CFA image according to the specific information. The associated image signal processor includes an input terminal, an operating unit and a processing unit, wherein the input terminal is for receiving an original CFA image and a pixel binned CFA image, the operating unit is for computing a specific information of the pixel binned CFA image, and the processing unit is for processing the original CFA image according to the specific information and utilizing the pixel binned CFA image.

Abstract: An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A photovoltaic electrochromic device and a method of manufacturing the same are provided. According to the method, at least one thin-film solar cell is formed on a transparent substrate, wherein the thin-film solar cell at least includes an anode, a photoelectric conversion layer, and a cathode, and a portion of a surface of the anode is exposed from the thin film solar cell. An electrochromic thin film is then deposited on at least one surface of the cathode and the exposed surface of the anode. Thereafter, an electrolyte layer is formed on a surface of the thin-film solar cell to cover the electrochromic thin film. The anode and the cathode of the thin-film solar cell also serve as the anode and the cathode of the photovoltaic electrochromic device.

Abstract: An embodiment of the invention provides a complex dye-sensitized photovoltaic apparatus including a conductive substrate, a counter electrode, a partition member, a photoelectric conversion layer, a first electrolyte, and a charge storage device or an electrochromic solution. A space is provided between the counter electrode and the conductive substrate. The partition member is disposed in the space, dividing the space into a first chamber and a second chamber. The photoelectric conversion layer is disposed on the conductive substrate in the first chamber filled with the first electrolyte, wherein the photoelectric conversion layer includes a porous semiconductor film and a dye absorbed on the porous semiconductor film. The photoelectric conversion layer and the conductive substrate form a working electrode. The charge storage device or the electrochromic solution is disposed in the second chamber.

Abstract: A liquid crystal display panel includes a transistor array substrate, a color filter substrate, a liquid crystal layer, and a sealant material. The transistor array substrate includes a transparent substrate, a transistor array, and a plurality of peripheral wires. The transparent substrate has a display region and a non-display region, and the non-display region is located beside the display region. The transistor array is disposed in the display region. The peripheral wires are disposed in the non-display region and electrically connected with the transistor array. A transmittance of the non-display region is less than 30%. The liquid crystal layer is disposed between the color filter substrate and the transistor array substrate. The sealant material is disposed in the non-display region and connected between the color filter substrate and the transistor array substrate. The sealant material surrounds the liquid crystal layer.