Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure, a front-side power rail in a front-side conductive layer, and a back-side power rail in a back-side conductive layer. The integrated circuit device also includes a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor, a back-side power node in the back-side conductive layer, and a top-to-bottom via-connector. The source conductive segment is conductively connected to the front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node.

Abstract: A method includes fabricating a first-type active-region semiconductor structure and second-type active-region semiconductor structure stacked with each other. The method also includes fabricating an upper source conductive segment intersecting the second-type active-region semiconductor structure at a second source region and forming a front-side power rail extending in a first direction that is conductively connected to the upper source conductive segment through a front-side terminal via-connector. The method further includes forming a top-to-bottom via-connector that passes through the substrate and conductively connects to the upper source conductive segment, forming a back-side metal layer on a backside of the substrate, and forming a back-side power node extending in the first direction that is conductively connected to the top-to-bottom via-connector.

Abstract: A method includes forming, over a substrate, adjacent first and second transistor stacks each including a first transistor, and a second transistor over the first transistor. A plurality of first conductive lines is formed in a first metal layer. The plurality of first conductive lines includes a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The power conductive line or the shielding conductive line is shared with the second transistor stack.

Abstract: A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, depositing a first conductive material over the set of transistors on a first level thereby forming a set of contacts for the set of transistors, fabricating a first set of vias over the set of transistors, depositing a second conductive material over the set of contacts on a second level thereby forming a set of power rails, depositing a third conductive material over the set of contacts on the second level thereby forming a first set of conductors, and depositing a fourth conductive material over the set of contacts on the second level thereby forming a second set of conductors. The set of power rails and the first set of conductors have the first width. The second set of conductors has a second width different from the first width.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method of making a semiconductor device includes forming a first device on a first side of a substrate, wherein the first device comprises a first source/drain (S/D) electrode. The method further includes forming a second device on a second side of the substrate, wherein the second side of the substrate is opposite the first side of the substrate, and the second device comprises a second S/D electrode. The method further includes forming a through substrate via (TSV) electrically connecting the first S/D electrode to the second S/D electrode, wherein a width of the TSV is equal to a width of at least one of the first S/D electrode or the second S/D electrode.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; two adjacent radiation-sensing regions formed in the substrate; and a trench isolation structure extending from the back surface of the substrate into the substrate between the two adjacent radiation-sensing regions. The trench isolation structure includes: a dielectric material; a first film being formed between the dielectric material and the substrate; a second film being formed between the first film and the dielectric material; and a third film being formed between the second film and the dielectric material. An electronegativity of the first film, an electronegativity of the second film and an electronegativity of the third film are different from each other.

Abstract: An integrated circuit (IC) structure includes a first transistor including a first gate structure adjacent to first and second portions of a first active area positioned in a semiconductor substrate, a second transistor including a second gate structure adjacent to the second portion of the first active area and a third portion of the first active area, an isolation structure overlying the second portion of the first active area, and first through third metal-like defined (MD) segments overlying the respective first through third portions of the first active area. The first and third MD segments are electrically connected to the respective first and third portions of the first active area, and the second MD segment is electrically isolated from the second portion of the first active area by the isolation structure.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Abstract: An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.

Abstract: A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.

Abstract: A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.