Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a stacked structure and contact vias. The stacked structure includes a plurality of conductive layers, and two adjacent conductive layers are isolated from each other with at least one dielectric layer. The contact vias have different heights, and partially through the stacked structure. Each of the plurality of contact vias is electrically connected to a corresponding conductive layer.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

Abstract: A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Abstract: A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

Abstract: The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.