Patents by Inventor Chih-Yu Lin

Chih-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366777
    Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.
    Type: Application
    Filed: January 29, 2021
    Publication date: November 25, 2021
    Inventors: Kun-Yu Lin, Yu-Ling KO, I-Chen CHEN, Chih-Teng LIAO, Yi-Jen CHEN
  • Publication number: 20210367058
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Application
    Filed: September 11, 2020
    Publication date: November 25, 2021
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20210367098
    Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Chien-Fu HUANG, Chih-Chiang LU, Chun-Yu LIN, Hsin-Chih CHIU
  • Publication number: 20210367059
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Application
    Filed: October 13, 2020
    Publication date: November 25, 2021
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Patent number: 11183474
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Publication number: 20210356810
    Abstract: Provided is a display device including: a backlight module; a first display panel disposed on the backlight module and including a first polarizer; and a second display panel disposed on the backlight module and including a second polarizer, wherein the first polarizer has a first projection, the second polarizer has a second projection, and an area of an overlap between the first projection and the second projection accounts for 10% or less of an area of the second projection, wherein the first display panel comprises a non-display area, and the second display panel corresponds in position to the non-display area.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Chih-Yu LIN, Kuan-Chou CHEN
  • Publication number: 20210358284
    Abstract: A visible-light-image physiological monitoring system with thermal detecting assistance is disclosed. The system takes a visible-light image and a thermal image of a body at the same time. A processing unit identifies a body feature of the visible-light image and determines a coordinate of the feature. In a learning mode, an initial temperature of the body feature is determined from the thermal image according to the coordinate of the body feature. After then, a physiological status monitoring mode is executed to monitor the temperature changes of the body feature and output an alarm when the temperature is determined to be abnormal. Therefore, a monitoring accuracy of the visible-light-image physiological monitoring system is increased and avoids transmitting false alarms or no alarms.
    Type: Application
    Filed: December 30, 2020
    Publication date: November 18, 2021
    Inventors: Chih-Hsin TSENG, Shih-Yun SHEN, Hsin-Yi LIN, Kang-Ning SHAN, Hsueh-Fa HSU, Por-Sau LIN, Chien-Yu CHEN, Tzu Ling LIANG, Huan-Yun WU, Yu-Chiao WANG, Chien-Hui HSU
  • Publication number: 20210359109
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: November 23, 2020
    Publication date: November 18, 2021
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11177430
    Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 16, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
  • Patent number: 11178756
    Abstract: A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 11176997
    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin
  • Patent number: 11177206
    Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 ?m.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 16, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chun-Te Lee, Chih-Ming Peng, Hui-Yu Huang, Yin-Chen Lin
  • Publication number: 20210350849
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Publication number: 20210349130
    Abstract: A method of inspecting power units applied to a plurality of power units is connected to a signal bus. The method is to disconnect the power unit having an output current from the signal bus, give a control command by a controller for raising the output current, measure the output current after the control command is given, and compare the measured output current with the target current value corresponding to the control command for determining an inspection result. The present disclosed example can effectively reduce inspection time and improve inspection accuracy.
    Type: Application
    Filed: September 9, 2020
    Publication date: November 11, 2021
    Inventors: Chih-Ming WU, Chien-Yu LIN, Tsung-Hsun LEE
  • Publication number: 20210351143
    Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hao CHENG, Yen-Yu CHEN, Chih-Wei LIN, Yi-Ming DAI
  • Publication number: 20210351281
    Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20210338414
    Abstract: A tissue repair device and a method for using the same are provided. The tissue repair device includes a body portion and at least one wire. The body portion includes an inner layer and an outer layer. The inner layer is close to a tissue, wherein the inner layer includes a hydrophilic structure, and the outer layer includes a hydrophobic structure. The wire is connected to the body portion to fix the body portion to the tissue.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Chieh HUANG, Jeng-Liang KUO, Hui-Ting HUANG, Shiun-Yin CHANG, Meng-Hsueh LIN, Cheng-Yi WU, Lih-Tao HSU, Pei-I TSAI, Hsin-Hsin SHEN, Chih-Yu CHEN, Kuo-Yi YANG, Chun-Hsien MA
  • Publication number: 20210343317
    Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Publication number: 20210345334
    Abstract: Various solutions for data transmission over multiple uplink carrier with respect to user equipment (UE) in mobile communications are described. A UE may establish a connection over a downlink component carrier and a first uplink component carrier with a network apparatus. The UE may further establish a connection over a second uplink component carrier with the network apparatus. The UE may transmit uplink data to the network apparatus via at least one of the first uplink component carrier and the second uplink component carrier. The UE may also assign the first uplink component carrier as a primary carrier and assigning the second uplink component carrier as a supplementary carrier. The UE may further switch the primary carrier from the first uplink component carrier to the second uplink component carrier.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Yih-Shen Chen, Shun-An Yang, Chih Hsiu Lin, Guan-Yu Lin
  • Publication number: 20210335720
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG