Abstract: An active stylus includes a stylus body and a touch sensor. The stylus body includes a first electrode and a pen body. The first electrode is used to send a signal. The pen body extends along a first direction. The touch sensor is provided on or in the pen body and includes a plurality of column electrodes extending along the first direction. There is a first gap between two adjacent column electrodes. Each column electrode has a first sensing electrode and a second sensing electrode. A first end of the first sensing electrode in the first direction has a recess to define a recess area. A second end of the second sensing electrode in the first direction has a projection extending into the recess area. There is a second gap between the projection and the recess. The second gap is smaller than the first gap.

Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

Abstract: The present application provides a transmission structure of an antenna and a proximity sensing circuit. The transmission structure includes a transmission line and at least one radio-frequency short-circuit element, a first coupling end of the transmission line is coupled to an antenna, and a second coupling end of the transmission line is coupled to a proximity sensing circuit, and the at least one radio-frequency short-circuit element is coupled between the transmission line and a ground, and is located between the antenna and the proximity sensing circuit. Utilizing the at least one radio-frequency short-circuit element in conjunction with the transmission line so that the transmission path between the antenna and the proximity sensing circuit has the high impedance, and hence preventing a radio-frequency signal from the antenna from affecting the sensing accuracy of the proximity sensing circuit.

Abstract: A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second r

Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.

Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of the SRAM in response to at least a first NOR output signal.

Abstract: A security extension design for non-volatile memory is shown. There is an in-system program loaded into the non-volatile memory. A memory controller downloads the in-system program to a data register to provide base firmware code, a function pointer structure and security firmware code on the data register. The memory controller executes the base firmware code, and security functions of the security firmware code are called by the base firmware code through information recorded in the function pointer structure and thereby the memory controller is switched to operate the non-volatile memory at a higher security level. The security firmware code uses an application programming interface (API) and is compatible with multiple projects.

Abstract: A physically unclonable function (PUF) generator includes a first sense amplifier that has a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The first sense amplifier is configured to compare accessing speeds of the first and second memory cells of the plurality of memory cells. Based on the comparison of the accessing speeds, the sense amplifier provides a first output signal for generating a PUF signature. A controller is configured to output an enable signal to the first sense amplifier, which has a first input terminal configured to receive a signal from a bit line of the first memory cell and a second input terminal configured to receive a signal from a bit line of the second memory cell.

Abstract: A display method adapted for an electronic device is provided. The method includes: identifying a target location of the last triggered target point on a screen, wherein the target point is triggered by an input operation applied on an I/O device of the electronic device; setting, according to an identified preset dividing pattern, a target dividing line on the screen based on the target location; identifying, according to an identified preset covering pattern, a target region and one or more non-target regions other than the target region of the screen based on the target dividing line; and adjusting the one or more non-target regions of the screens to decrease the readability of the one or more non-target regions.

Abstract: Provided is a display device including: a backlight module; a first display panel disposed on the backlight module and including a first polarizer; and a second display panel disposed on the backlight module and including a second polarizer, wherein the first polarizer has a first projection, the second polarizer has a second projection, and an area of an overlap between the first projection and the second projection accounts for 10% or less of an area of the second projection, wherein the first display panel comprises a non-display area, and the second display panel corresponds in position to the non-display area.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Abstract: A static random access memory (SRAM) circuit can group the column bit lines in a memory array into subsets of bit lines, and a y-address signal input is provided for each subset of bit lines. Additionally or alternatively, each row in the array of memory cells is operably connected to multiple word lines.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

Abstract: Provided is a display device including: a backlight module; a first display panel disposed on the backlight module and including a first polarizer; and a second display panel disposed on the backlight module and including a second polarizer, wherein the first polarizer has a first projection, the second polarizer has a second projection, and an area of an overlap between the first projection and the second projection accounts for 10% or less of an area of the second projection.

Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.