Patents by Inventor Chih Yu

Chih Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices having merged source/drain features and methods of fabrication thereof
    Patent number: 11705371
    Abstract: Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Chung-Hsien Yeh, Chih-Yu Ma
  • Polarization enhancement structure for enlarging memory window
    Patent number: 11705516
    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Chang, Mauricio Manfrini, Hung Wei Li, Yu-Ming Lin
  • Inductor structure
    Patent number: 11699550
    Abstract: An inductor structure includes a first curve metal component, a second curve metal component, a connection component, and a capacitor. The first and the second curve metal components are disposed on a layer. The layer is located at a first plane, the first and the second curve metal components are located at a second plane. The connection component is coupled to the first curve metal component and the second curve metal component. A first terminal of the connection component is coupled to a first terminal of the first curve metal component. A second terminal of the connection component is coupled to a first terminal of the second curve metal component. A first terminal of the capacitor is coupled to a second terminal of the first curve metal component. A second terminal of the capacitor is coupled to a second terminal of the second curve metal component.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: July 11, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Chih-Yu Tsai, Kai-Yi Huang
  • Computer System for Failing a Secure Boot in a Case Tampering Event
    Publication number: 20230214492
    Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Moxa Inc.
    Inventors: Chia-Te Chou, Tsung-Yi Lin, YOONG TAK TAN, Hsin-Ju Wu, Jian-Yu Liao, Che-Yu Huang, Tsung-Li Fang, Kuo-Chen Wu, Chih-Yu Chen
  • Computer System for Failing a Secure Boot in a Case Tampering Event
    Publication number: 20230214493
    Abstract: A computer system for failing a secure boot in a case tampering event comprises a trusted platform module (TPM), for generating a plurality of random bytes for a secure boot of the computer system; a bootloader, for storing information in at least one hardware of the computer system and performing the secure boot, wherein the information comprises the plurality of random bytes, and the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, for detecting a case tampering event in the computer system, and transmitting a signal for triggering a deletion of the plurality of random bytes, if the case tampering event happens in the computer system. The bootloader or the OS performs the operation of deleting the plurality of random bytes stored in the at least one hardware to fail the secure boot, in response to the signal.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Moxa Inc.
    Inventors: YOONG TAK TAN, Chih-Yu Chen, Che-Yu Huang, Hsin-Ju Wu, Tsung-Yuan Wu, Tzung-Fu Tsai, Kuo-Chen Wu, Jian-Yu Liao, Tsung-Li Fang
  • DEVICE AND METHOD FOR DECODING VIDEO DATA
    Publication number: 20230217019
    Abstract: A method of decoding video data by an electronic device is provided. The electronic device determines a block unit from an image frame according to the video data. The electronic device determines, for the block unit, a first mode list including intra candidate modes selected from intra default modes, and predicts at least one template region adjacent to the block unit to generate template predictions based on intra template modes. Each of the intra template modes indicates one of the intra candidate modes and one of template reference lines, and the template reference lines include at least one template neighboring line nonadjacent to the at least one template region. The electronic device determines a template cost value between the at least one template region and each of the template predictions, and reconstructs the block unit based on a second mode list determined based on the template cost values.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 6, 2023
    Inventors: CHIH-YU TENG, YU-CHIAO YANG
  • Memory array gate structures
    Patent number: 11695073
    Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Proximity sensor and proximity sensing method
    Patent number: 11693519
    Abstract: The present invention relates to a proximity sensor and a proximity sensing method. The proximity sensor includes a sensing element and a sensing circuit. The sensing circuit is coupled to the sensing element and transmits a first driving signal and a second signal to the sensing element, respectively. The sensing element receives the first driving signal and the second driving signal, respectively, and generates a first sensing signal and a second sensing signal, respectively. The sensing circuit generates a proximity signal according to the first sensing signal and the second sensing signal. Therefore, the present invention may improve the accuracy of sensing the proximity of the human body whether near to the sensor.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 4, 2023
    Assignee: Sensortek Technology Corp.
    Inventor: Chih-Yu Lin
  • Method and system for audio recognition of arcing during semiconductor process
    Patent number: 11688413
    Abstract: An arcing detection system detects arcing within a semiconductor processing cleanroom environment. The arcing detection system includes an array of microphones positioned within the cleanroom environment. The microphones receive soundwaves within the cleanroom environment and generate audio signals based on the sound waves. The arcing system includes a control system that receives the audio signals from the microphones. The control system analyzes the audio signals and detects arcing within the cleanroom environment based on the audio signals. The control system can adjust a semiconductor process in real time responsive to detecting arcing.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Yu Wang
  • Semiconductor device with treated interfacial layer on silicon germanium
    Patent number: 11688812
    Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Chang, Hsiang-Pi Chang, Zi-Wei Fang
  • Disaggregation driving sequences for four particle electrophoretic displays
    Patent number: 11688357
    Abstract: The present invention provides improved driving methods for four particle electrophoretic displays that improves the performance of such displays when they are deployed in low temperature environments and the displays are required to be updated when positioned vertically (i.e., the driving electric fields are substantially perpendicular to the direction of Earth's gravity). Methods are provided for displaying each of the colors at each pixel, as desired, with minimal interference (contamination) from the other particles.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: June 27, 2023
    Assignee: E Ink California, LLC
    Inventors: Ning-Wei Jan, Chen-Kai Chiu, Feng-Shou Lin, Chih-Yu Cheng
  • LAYOUT OF SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20230197153
    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
    Type: Application
    Filed: January 20, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Chun-Hsien Huang, Hsin-Chih Yu, Meng-Ping Chuang, Li-Ping Huang, Yu-Fang Chen
  • Recognition method for photolithography process and semiconductor device
    Patent number: 11682557
    Abstract: A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: June 20, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Yu Chiang
  • Semiconductor FinFET Device and Method
    Publication number: 20230187216
    Abstract: A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 15, 2023
    Inventor: Chih-Yu Wang
  • SYSTEM AND METHOD FOR MONITORING CHEMICAL MECHANICAL POLISHING
    Publication number: 20230182257
    Abstract: An apparatus for chemical mechanical polishing of a wafer includes a process chamber and a rotatable platen disposed inside the process chamber. A polishing pad is disposed on the platen and a wafer carrier is disposed on the platen. A slurry supply port is configured to supply slurry on the platen. A process controller is configured to control operation of the apparatus. A set of microphones is disposed inside the process chamber. The set of microphones is arranged to detect sound in the process chamber during operation of the apparatus and transmit an electrical signal corresponding to the detected sound. A signal processor is configured to receive the electrical signal from the set of microphones, process the electrical signal to enable detection of an event during operation of the apparatus, and in response to detecting the event, transmit a feedback signal to the process controller.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 15, 2023
    Inventors: Chih-Yu WANG, Tien-Wen WANG, In-Tsang LIN, Hsin-Hui CHOU
  • Method and image processing device for mura detection on display
    Patent number: 11676265
    Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. An original image of the display is received and segmented into region of interest (ROI) patches. A predetermined range of spatial frequency components are filtered out from the ROI patches to generate filtered ROI patches. A mura defect is identified from the display according to the filtered ROI patches and predetermined mura patterns.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 13, 2023
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Yu Chu, Po-Yuan Hsieh, Chieh-En Lee, Chung-Hao Tien, Shih-Hsuan Chen
  • Static random access memory with a supplementary driver circuit and method of controlling the same
    Patent number: 11676660
    Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
  • Interconnect structure
    Patent number: 11676853
    Abstract: A method includes: forming a first conductive structure in a first dielectric layer; forming a conductive protection structure that is coupled to at least part of the first conductive structure; forming a second dielectric layer over the first dielectric layer; forming a via hole extending through at least part of the second dielectric layer to expose a portion of the conductive protection structure; cleaning the via hole; and refilling the via hole with a conductive material to form a via structure.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chih Yu, Chien-Mao Chen
  • CURRENT COLLECTOR PROTECTIVE GLUE
    Publication number: 20230174832
    Abstract: A current collector protective glue includes a solvent and an adhesive. The solvent is selected from one or more of water, ethanol, NMP, acetone, and butanone. The adhesive is selected from one or more of cellulose, polyacrylic acid, styrene-butadiene rubber, styrene butadiene rubber, and nitrile rubber.
    Type: Application
    Filed: November 8, 2022
    Publication date: June 8, 2023
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Wei Chen Huang, Chih-Yu Yang
  • MAXIMUM CURRENT SUPPRESSION FOR POWER MANAGEMENT IN A MULTI-CORE SYSTEM
    Publication number: 20230176645
    Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
    Type: Application
    Filed: July 16, 2022
    Publication date: June 8, 2023
    Inventors: Hung-Wei Wu, Chih-Yu Chang