Abstract: A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure is disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.

Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Abstract: A computing device prompts a user to place the user’s hand including a wrist next to a facial region of the user. The computing device obtains an image depicting the facial region and a wrist of the user. The computing device measures a diameter of an iris in the facial region depicted in the image and measures a width of a wrist of the hand depicted in the image. The computing device estimates an actual wrist width of the user’s hand based on an actual iris diameter, the measured diameter of the iris in the facial region depicted in the image, and the measured width of the wrist of the hand depicted in the image.

Abstract: In a method for detecting carpal tunnel using an ultrasonic detection device, the palm is placed on a flat surface, and the fingers are naturally stretched out to form a “5” shape; a mark is placed 0.5 cm above the crease of the palm (Distal wrist crease), and the probe unit of an ultrasonic detection device is placed at the short axis position of the wrist joint. By rotating the probe unit, the probe unit, the marker, and the index finger are on the same axis (index finger axis), so that the image of the carpal tunnel section of the palm can be obtained on a display of the ultrasonic detection device. Accordingly, the detection method is accurate and efficient, correctly guides students and doctors to find the position of the carpal tunnel correctly, and avoids the purposeless search for the position of the carpal tunnel by the probe on the palm, and subsequent treatment.

Abstract: Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

Abstract: A charged particle beam apparatus for inspecting a sample is provided. The apparatus includes a pixelized electron detector to receive signal electrons generated in response to an incidence of an emitted charged particle beam onto the sample. The pixelized electron detector includes multiple pixels arranged in a grid pattern. The multiple pixels may be configured to generate multiple detection signals, wherein each detection signal corresponds to the signal electrons received by a corresponding pixel of the pixelized electron detector. The apparatus further includes a controller includes circuitry configured to determine a topographical characteristic of a structure within the sample based on the detection signals generated by the multiple pixels, and identifying a defect within the sample based on the topographical characteristic of the structure of the sample.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

Abstract: A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Abstract: A method includes: forming a first conductive structure in a first dielectric layer; forming a conductive protection structure that is coupled to at least part of the first conductive structure; forming a second dielectric layer over the first dielectric layer; forming a via hole extending through at least part of the second dielectric layer to expose a portion of the conductive protection structure; cleaning the via hole; and refilling the via hole with a conductive material to form a via structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate dielectric layer over a substrate. The method includes forming a work function metal layer over the gate dielectric layer. The method includes forming a glue layer over the work function metal layer. The glue layer is thinner than the gate dielectric layer. The method includes forming a gate electrode over the glue layer. The gate electrode includes fluorine. The method includes annealing the gate electrode. The fluorine diffuses from the gate electrode into the gate dielectric layer.

Abstract: Provided herein are compounds which are useful as antagonists of the muscarinic acetylcholine receptor M1 (mAChR M1); synthetic methods for making the compounds; pharmaceutical compositions comprising the compounds; and methods of treating neurological and psychiatric disorders associated with muscarinic acetylcholine receptor dysfunction using the compounds and compositions.

Abstract: A method of applying heat to living tissue mainly uses a device for performing heat treatment on at least a portion of the living tissue in high-low-high temperature steps. In high temperature step, the temperature of the at least a portion of the living tissue is heated and kept between 39-46° C., and the heating period is no longer than 30 minutes. In low temperature step, the at least a portion of the living tissue is cooled, and the low temperature period should not be greater than a natural cooling time interval. In addition, the low temperature period must also be shorter than the heating period. Thus, the present invention allows the abnormal cells to be selectively restored or apoptotic without damaging the normal cells.

Abstract: A heat-dissipation device with detachability against the adhesion of a paste includes a heat-dissipation structure and a detachment device. The heat-dissipation structure installed on a heat-generating component includes a base, and a heat-dissipation element disposed on the base, and a through hole penetrating through the base. The detachment device includes a housing disposed on the base and covering the through hole, wherein the housing includes a gas chamber, and a gas hole connected to the gas chamber, the gas hole being in communication with the through hole. An adjustment element is movably disposed in the gas chamber. A gas in the housing is pushed out through the gas hole by moving the adjustment element downwards, creating a positive gas pressure and thus forcing a separation between the heat-dissipation structure and the heat-generating component on which the structure is installed.