Patents by Inventor Chih Yu

Chih Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE WITH TREATED INTERFACIAL LAYER ON SILICON GERMANIUM
    Publication number: 20230282753
    Abstract: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu CHANG, Hsiang-Pi CHANG, Zi-Wei FANG
  • Mouse
    Patent number: 11740711
    Abstract: A mouse includes a main housing, a key structure, and a pressing force adjusting component. The key structure has a connecting end, a free end, and an elastic section. The connecting end is connected to the main housing, and the elastic section is located between the connecting end and the free end. The pressing force adjusting component is movably disposed on the main housing and has a limiting portion, and the limiting portion limits elastic deformation of the elastic section. A location of the pressing force adjusting component on the main housing is adapted to be changed to change a location of the limiting portion at the elastic section.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: August 29, 2023
    Assignee: Chicony Electronics Co., Ltd.
    Inventor: Wei-Chih Yu
  • Bicyclic compounds and their use in the treatment of cancer
    Patent number: 11738009
    Abstract: The present disclosure is directed to novel compounds of Formula I and pharmaceutically acceptable salts, solvates, solvates of the salt and prodrugs thereof, useful in the prevention (e.g., delaying the onset of or reducing the risk of developing) and treatment (e.g., controlling, alleviating, or slowing the progression of) of cancer, including glioblastoma, bone cancer, head and neck cancer, melanoma, basal cell carcinoma, squamous cell carcinoma, adenocarcinoma, oral cancer, esophageal cancer, gastric cancer, intestinal cancer, colon cancer, bladder cancer, hepatocellular carcinoma, renal cell carcinoma, pancreatic cancer, ovarian cancer, cervical cancer, lung cancer, breast cancer, and prostate cancer. The compounds of the disclosure are selective antagonists of the EP4 receptor and useful treatment of various diseases that may be ameliorated with blockade of PGE2-mediated signaling.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 29, 2023
    Assignee: TEMPEST THERAPEUTICS, INC.
    Inventors: Yalda Bravo, Jason David Burch, Austin Chih-Yu Chen, Joe Fred Nagamizo
  • SYSTEM FOR SETTING STORING POSITIONS OF TIRES AND METHOD FOR THE SAME
    Publication number: 20230264525
    Abstract: A method for storing positions of tires and a system for the same are disclosed. The method includes inputting information for a tire by a hand held tool. Transmitting the information for the tire and a storing position of the tire to a remote server, and generating an index information including the storing position of the tire by the remote server. Accordingly, the storing position of the tire can be conveniently inquired, such that the time-consuming of changing the tires of vehicle can be effectively reduced.
    Type: Application
    Filed: December 2, 2022
    Publication date: August 24, 2023
    Inventors: HUNG-CHIH YU, JIAN-ZHI WANG, MING-YUNG HUANG
  • SEMICONDUCTOR CELL AND ACTIVE AREA ARRANGEMENT
    Publication number: 20230268339
    Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 24, 2023
    Inventors: Pochun Wang, Chih-Yu LAI, Chi-Yu Lu, Shang-Hsuan CHIU, Hui-Zhong Zhuang, Chih-Liang Chen
  • NOVEL THIN FILM RESISTOR
    Publication number: 20230268340
    Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Hung-Chih YU, Chien-Mao Chen
  • Devices for vehicle message management
    Patent number: 11734652
    Abstract: A vehicle message managing method includes: providing an operation message of a tire through a tire sensor; receiving the operation message through the tire sensor setting tool, or receiving at least one outer message through the tire sensor setting tool; transmitting at least one of the operation message and the outer message to a remote server; storing and analyzing at least one of the operation message and the outer message and generating an analyzing result.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: August 22, 2023
    Assignee: ORANGE ELECTRONIC CO., LTD.
    Inventors: Chin-Yao Hsu, Hung-Chih Yu, Jia-Hao Bai
  • Post gate dielectric processing for semiconductor device fabrication
    Patent number: 11735484
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Cheng Hong Yang, Shih-Hao Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • DISAGGREGATION DRIVING SEQUENCES FOR FOUR PARTICLE ELECTROPHORETIC DISPLAYS
    Publication number: 20230260471
    Abstract: The present invention provides improved driving methods for four particle electrophoretic displays that improves the performance of such displays when they are deployed in low temperature environments and the displays are required to be updated when positioned vertically (i.e., the driving electric fields are substantially perpendicular to the direction of Earth's gravity). Methods are provided for displaying each of the colors at each pixel, as desired, with minimal interference (contamination) from the other particles.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: NING-WEI JAN, CHEN-KAI CHIU, FENG-SHOU LIN, CHIH-YU CHENG
  • LOW RANDOM TELEGRAPH NOISE DEVICE
    Publication number: 20230261087
    Abstract: A semiconductor device includes an active area with a source and a drain, a gate oxide disposed on a portion of the active area between the source and the drain, and a gate is disposed over the gate oxide. In a noise suppressing structure, edge oxide regions are disposed on the gate oxide with edges of the edge oxide regions coinciding with the active area edges, and the gate is disposed over the edge oxide regions. In another noise suppressing structure, first and second active area edge extensions of respective first and second active area edges increase a width in the transverse direction of the active area at the edge extensions to a width greater than a minimum width of the active area in the transverse direction. The gate does not completely cover the first and second active area edge extensions along the channel direction.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Chih-Yu Tseng, Chung-Wen Weng
  • Ferroelectric memory device and method of forming the same
    Patent number: 11729986
    Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • 3D stackable memory and methods of manufacture
    Patent number: 11729997
    Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin
  • Dopant concentration boost in epitaxially formed material
    Patent number: 11721760
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • Three-dimensional memory device and method
    Patent number: 11716856
    Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Meng-Han Lin, Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin
  • Grip Exerciser
    Publication number: 20230233904
    Abstract: A grip exerciser has a first handle, a second handle, a connecting member and a spring.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventor: CHIH-YU HSU
  • MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230238056
    Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsin NIEN, Hidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN
  • LITHIUM BATTERY SYSTEM AND CHARGE-DISCHARGE METHOD OF THE SAME
    Publication number: 20230238594
    Abstract: A lithium battery system is provided. The lithium battery system comprises a battery pack, a battery management module, and a cooling control module. The battery pack comprises a first battery module and a second battery module having different battery characteristics. The battery management module is electrically connected to the battery pack, and configured to control an operating condition of the battery pack according to the battery characteristics of the first battery module and the second battery module. The cooling control module is electrically connected to the battery management module and the battery pack, and configured to cool the battery pack according to an instruction of the battery management module. The application combines a variety of lithium batteries with different performances to obtain a lithium battery system with excellent comprehensive performance.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 27, 2023
    Inventors: CHUN-HSIEN CHO, KUO-CHIH YU, LI-TING CAI
  • Method of manufacturing at least one semiconductor device on or in a base semiconductor material disposed in a containment structure including a buried layer
    Patent number: 11710632
    Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Hung-Te Lin, Hung-Chih Yu, Chia-Wei Liu
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20230230837
    Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.
    Type: Application
    Filed: January 3, 2022
    Publication date: July 20, 2023
    Applicant: Winbond Electronics Corp.
    Inventor: Chih-Yu CHIANG
  • Semiconductor device extension insulation
    Patent number: 11705393
    Abstract: A semiconductor device includes: a plurality of vertical conductive structures, wherein each of the plurality of vertical conductive structures extends through an isolation layer; and an insulated extension disposed horizontally between a first one and a second one of the plurality of vertical conductive structures.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chih Yu, Chien-Mao Chen