Patents by Inventor Chih Yuan Chang

Chih Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11141715
    Abstract: The present disclosure provides a method for fabricating a heterogeneous nickel-based catalyst on an aluminum oxide support. The method includes a solution preparation step, a drop-cast step, a first calcining step, and a second calcining step. The solution preparation step is provided for preparing a precursor solution. The drop-cast step is provided for dropping the precursor on the support. The first calcining step is provided for obtaining an oxidation state catalyst. The second calcining step is provided for obtaining the heterogeneous nickel-based catalysts on aluminum oxide support.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 12, 2021
    Assignees: National Tsing Hua University, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., Ltd., Darien Chemical Corp.
    Inventors: De-Hao Tsai, Hung-Yen Chang, Guan-Hung Lai, Chih-Yuan Lin, Chun-Yu Lee, Chih-Cheng Chia, Chuen-Lih Hwang, Huan-Ming Chang
  • Publication number: 20210313396
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 11139274
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Publication number: 20210305213
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
  • Patent number: 11114543
    Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hong Chang, Chih-Yuan Chan, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
  • Publication number: 20210256236
    Abstract: A fingerprint detecting system comprises a fingerprint module, for detecting a fingerprint of a user and outputting a current signal according to the detected fingerprint, and a signal processing circuit, coupled to the fingerprint module, for receiving the current signal from the fingerprint module, performing a offset cancellation for the current signal to remove an offset of the current signal, and converting the current signal without the offset to a voltage signal for fingerprint data analysis.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Hung-Kai Chen, Ting-Hsuan Hung, Chih-Yuan Chang, Feng-Lin Chan
  • Publication number: 20210256240
    Abstract: A fingerprint detecting system comprises a fingerprint module, for receiving a fingerprint driving signal and performing a frequency modulation on the fingerprint driving signal, to correspondingly outputting a fingerprint signal with a first frequency based on the fingerprint driving signal, and a signal processing circuit, coupled to the fingerprint module, for receiving the fingerprint signal with the first frequency, performing a frequency demodulation to shift the first frequency of the fingerprint signal to a second frequency, and filtering the fingerprint signal with the second frequency based on the first frequency, whereby the filtered fingerprint signal is used for a fingerprint data analysis.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Hung-Kai Chen, Ting-Hsuan Hung, Chih-Yuan Chang, Feng-Lin Chan
  • Patent number: 11095065
    Abstract: A power supply device includes a housing having a socket opening, and a pair of sliding grooves are formed on the socket opening. A guiding piece is formed at a bottom of each sliding groove, and the guiding piece includes a positioning section and a guiding section. A power socket passes through the sliding grooves along the guiding section, and one side of the power socket is abutted against the positioning section so as to contact the socket opening. A cover plate is provided with a pair of clips corresponding to the sliding grooves, and the clips are inserted into the pair of sliding grooves and abutted against a side of the power socket for positioning the power socket.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: August 17, 2021
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventor: Chih-Yuan Chang
  • Patent number: 11094634
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 11075136
    Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
  • Publication number: 20210226373
    Abstract: A power supply device includes a housing having a socket opening, and a pair of sliding grooves are formed on the socket opening. A guiding piece is formed at a bottom of each sliding groove, and the guiding piece includes a positioning section and a guiding section. A power socket passes through the sliding grooves along the guiding section, and one side of the power socket is abutted against the positioning section so as to contact the socket opening. A cover plate is provided with a pair of clips corresponding to the sliding grooves, and the clips are inserted into the pair of sliding grooves and abutted against a side of the power socket for positioning the power socket.
    Type: Application
    Filed: July 18, 2020
    Publication date: July 22, 2021
    Inventor: Chih-Yuan CHANG
  • Patent number: 11062650
    Abstract: A sensing circuit of a display device is provided. The sensing circuit includes a chopper circuit, a first operational amplifier and a filter. The chopper circuit is configured to receive a sensing input signal of the display device and modulate the sensing input signal. The first operational amplifier is coupled to the chopper circuit. The first operational amplifier is configured to receive the modulated sensing input signal and output the modulated sensing input signal to the chopper circuit. The chopper circuit is further configured to demodulate the modulated sensing input signal from the first operational amplifier and output the demodulated sensing input signal. The filter is coupled to the chopper circuit. The filter is configured to filter the demodulated sensing input signal from the chopper circuit and output the filtered sensing input signal as a sensing output signal. A source driver including the sensing circuit is also provided.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 13, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Yuan Chang, Feng-Lin Chan
  • Patent number: 11063016
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Publication number: 20210206687
    Abstract: Disclosed herein is a glass composition that includes, based on the total weight of the composition, 52 wt % to 58 wt % of SiO2, 12 wt % to 16 wt. of Al2O3, 16 wt % to 26 wt % of B2O3, greater than 0 wt % and not greater than 2 wt % of MgO, 1 wt % to 6 wt % of CaO, greater than 1 wt % and lower than 5 wt % of TiO2, greater than 0 wt % and not greater than 0.6 wt % of Na2O, 0 wt % to 0.5 wt % of K2O, 0 wt % to 1 wt % of F2, 1 wt % to 5 wt % of ZnO, greater than 0 wt % and not greater than 1 wt % of Fe2O3; and 0.1 wt % to 0.6 wt % of SO3. Also disclosed herein is a glass fiber including the glass composition.
    Type: Application
    Filed: November 20, 2020
    Publication date: July 8, 2021
    Inventors: Wen-Ho HSU, Bih-Cherng CHERN, Chih-Yuan CHANG, Yueh-Heng LEE, Wei-Chih LO
  • Publication number: 20210193621
    Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventor: Chih Yuan Chang
  • Publication number: 20210125960
    Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Chih-Yuan Chang
  • Publication number: 20210090498
    Abstract: A sensing circuit of a display device is provided. The sensing circuit includes a chopper circuit, a first operational amplifier and a filter. The chopper circuit is configured to receive a sensing input signal of the display device and modulate the sensing input signal. The first operational amplifier is coupled to the chopper circuit. The first operational amplifier is configured to receive the modulated sensing input signal and output the modulated sensing input signal to the chopper circuit. The chopper circuit is further configured to demodulate the modulated sensing input signal from the first operational amplifier and output the demodulated sensing input signal. The filter is coupled to the chopper circuit. The filter is configured to filter the demodulated sensing input signal from the chopper circuit and output the filtered sensing input signal as a sensing output signal. A source driver including the sensing circuit is also provided.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chih-Yuan Chang, Feng-Lin Chan
  • Publication number: 20200402847
    Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.
    Type: Application
    Filed: August 29, 2020
    Publication date: December 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
  • Publication number: 20200321288
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Publication number: 20200286845
    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: CHUEI-TANG WANG, CHIH-CHIEH CHANG, YU-KUANG LIAO, HSING-KUO HSIA, CHIH-YUAN CHANG, JENG-SHIEN HSIEH, CHEN-HUA YU