Patents by Inventor Chih Yuh Yang
Chih Yuh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622370Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: September 25, 2015Date of Patent: April 14, 2020Assignee: Monterey Research, LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 9276007Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: January 29, 2014Date of Patent: March 1, 2016Assignee: Cypress Semiconductor CorporationInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 9245895Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: July 26, 2011Date of Patent: January 26, 2016Assignee: Cypress Semiconductor CorporationInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Publication number: 20140312409Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: ApplicationFiled: January 29, 2014Publication date: October 23, 2014Applicant: SPANSION LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 8642441Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: December 15, 2006Date of Patent: February 4, 2014Assignee: Spansion LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Harpreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Publication number: 20110278660Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: SPANSION LLCInventors: Ning Cheng, K.T. Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 8012830Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: August 8, 2007Date of Patent: September 6, 2011Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 7951675Abstract: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.Type: GrantFiled: December 17, 2007Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Lei Xue, Aimin Xing, Chih-Yuh Yang, Angela Hui, Chungho Lee
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Patent number: 7915160Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.Type: GrantFiled: January 19, 2007Date of Patent: March 29, 2011Assignee: GlobalFoundries Inc.Inventors: Cyrus E. Tabery, Srikanteswara Dakshina-Murthy, Chih-Yuh Yang, Bin Yu
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Patent number: 7867848Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.Type: GrantFiled: April 22, 2010Date of Patent: January 11, 2011Assignee: Spansion, LLCInventors: Minghao Shen, Fred Cheung, Ning Cheung, Wei Zheng, Hiroyuki Kinoshita, Chih-Yuh Yang
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Publication number: 20100203694Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.Type: ApplicationFiled: April 22, 2010Publication date: August 12, 2010Inventors: Minghao SHEN, Fred CHEUNG, Ning CHEUNG, Wei ZHENG, Hiroyuki KINOSHITA, Chih-Yuh YANG
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Patent number: 7732281Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.Type: GrantFiled: April 24, 2006Date of Patent: June 8, 2010Assignee: Spansion LLCInventors: Minghao Shen, Fred Cheung, Ning Cheng, Wei Zheng, Hiroyuki Kinoshita, Chih-Yuh Yang
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Patent number: 7696038Abstract: Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.Type: GrantFiled: April 26, 2006Date of Patent: April 13, 2010Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiroyuki Kinoshita, Timothy Thurgate, Wei Zheng, Ashot Melik-Martirosian, Angela Hui, Chih-Yuh Yang
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Patent number: 7675104Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.Type: GrantFiled: July 31, 2006Date of Patent: March 9, 2010Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
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Publication number: 20090152669Abstract: Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Lei Xue, Aimin Xing, Chih-Yuh Yang, Angela Hui, Chungho Lee
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Publication number: 20090039405Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Applicant: SPANSION LLCInventors: Ning Cheng, K.T. Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Publication number: 20080023751Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
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Patent number: 7268066Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.Type: GrantFiled: August 19, 2004Date of Patent: September 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Christopher F. Lyons
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Patent number: 7183223Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.Type: GrantFiled: December 8, 2003Date of Patent: February 27, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Cyrus E. Tabery, Srikanteswara Dakshina-Murthy, Chih-Yuh Yang, Bin Yu
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Patent number: 7183152Abstract: A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.Type: GrantFiled: October 29, 2004Date of Patent: February 27, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Chih-Yuh Yang, Bin Yu