Patents by Inventor Chih Yuh Yang
Chih Yuh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6323093Abstract: A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the hard-mask. The oxidation process is carried out by selectively oxidizing an oxidizable layer overlying an etch-stop layer. Upon completion of the oxidation process, the etch-stop layer is removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.Type: GrantFiled: April 12, 1999Date of Patent: November 27, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Scott Allan Bell, Chih-Yuh Yang
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Publication number: 20010038972Abstract: A method of forming a shallow trench isolation is provided. In the method, a barrier oxide layer is formed on a substrate, and a silicon nitride layer is formed on the barrier oxide layer. A metal layer is formed on the silicon nitride layer, and an ultra-thin photoresist is formed on the metal layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a shallow trench. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the shallow trench pattern to the metal layer. The first etch step includes an etch chemistry that is selective to the metal layer over the ultra-thin photoresist layer. The metal layer is used as a hard mask during a second etch step to form the shallow trench by etching portions of the silicon nitride layer, barrier oxide layer and substrate.Type: ApplicationFiled: November 20, 1998Publication date: November 8, 2001Applicant: Christopher F. LyonsInventors: CHRISTOPHER F. LYONS, SCOTT A. BELL, HARRY J. LEVINSON, KHANH B. NGUYEN, FEI WANG, CHIH YUH YANG
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Patent number: 6309926Abstract: A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.Type: GrantFiled: December 4, 1998Date of Patent: October 30, 2001Assignee: Advanced Micro DevicesInventors: Scott A. Bell, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Chih Yuh Yang
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Patent number: 6306560Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon oxynitride layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon oxynitride layer; etching the exposed portion of the silicon oxynitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: October 23, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6287918Abstract: A process for fabricating a semiconductor device includes the formation of a metal device feature layer using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the metal device feature. The oxidation process is carried out by selectively, laterally oxidizing the metal composition of the device feature that overlies a dielectric layer. The lateral oxidation process forms metal oxide sidewall spacers on the device feature. Upon completion of the oxidation process, the metal oxide sidewall spacers are removed and a residual layer of unoxidized metal remains. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.Type: GrantFiled: April 12, 1999Date of Patent: September 11, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Scott Allan Bell, Chih-Yuh Yang
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Publication number: 20010014512Abstract: In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.Type: ApplicationFiled: September 17, 1999Publication date: August 16, 2001Inventors: CHRISTOPHER F. LYONS, SCOTT A. BELL, HARRY J. LEVINSON, KHANH B. NGUYEN, FEI WANG, CHIH YUH YANG
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Patent number: 6214683Abstract: A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a lateral oxidation process to reduce the lateral dimension of the hard-mask. The lateral oxidation is carried out by selectively oxidizing an oxidizable layer situated between an etch-stop layer and an oxidation resistant layer. Upon completion of the lateral oxidation process, etch-stop layer and the oxidation resistant are removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.Type: GrantFiled: April 12, 1999Date of Patent: April 10, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Scott Allan Bell, Chih-Yuh Yang
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Patent number: 6211044Abstract: A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reacting a reaction layer situated between an etch-stop layer and a reaction resistant layer. Upon completion of the chemical reaction process, the etch-stop layer and the reaction resistant layer is removed, and a residual layer of unreacted material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.Type: GrantFiled: April 12, 1999Date of Patent: April 3, 2001Assignee: Advanced Micro DevicesInventors: Qi Xiang, Scott Allan Bell, Chih-Yuh Yang
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Patent number: 6200884Abstract: A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.Type: GrantFiled: July 31, 1999Date of Patent: March 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Chih-Yuh Yang, Mark S. Chang
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Patent number: 6200907Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: March 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6184128Abstract: In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second phoType: GrantFiled: January 31, 2000Date of Patent: February 6, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6171763Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, a silicon nitride layer over the metal layer, and an oxide layer over the silicon nitride layer; depositing an ultra-thin photoresist over the oxide layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6165695Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: December 1, 1998Date of Patent: December 26, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Patent number: 6162587Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: December 1, 1998Date of Patent: December 19, 2000Assignee: Advanced Micro DevicesInventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Patent number: 6156658Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: December 5, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6140023Abstract: A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.Type: GrantFiled: December 1, 1998Date of Patent: October 31, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Levinson, Scott A. Bell, Christopher F. Lyons, Khanh B. Nguyen, Fei Wang, Chih Yuh Yang
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Patent number: 6133129Abstract: A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure.Type: GrantFiled: May 7, 1999Date of Patent: October 17, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Scott A. Bell, Chih-Yuh Yang
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Patent number: 6127070Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer and the dielectric layer. The nitride layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: December 1, 1998Date of Patent: October 3, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Patent number: 6121155Abstract: The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.Type: GrantFiled: December 4, 1998Date of Patent: September 19, 2000Assignee: Advanced Micro DevicesInventors: Chih-Yuh Yang, Scott Bell, Qi Xiang
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Patent number: 6107172Abstract: A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.Type: GrantFiled: August 1, 1997Date of Patent: August 22, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Chih-Yuh Yang, Scott A. Bell, Daniel Steckert