Abstract: Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

Abstract: A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal.

Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon nitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon nitride layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Abstract: During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

Abstract: A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.