Abstract: A process forms alternating first and second metal lines in an interlevel dielectric layer. A first photolithography and etching process forms trenches in a patterning layer. A plurality of dielectric spacers are formed on sidewalls of the trenches. A second photolithography and etching process forms a pattern of the first metal lines in a hard mask layer between the interlevel dielectric layer and the patterning layer based on the dielectric spacers. A third photolithography and etching process forms a pattern of a second metal lines in the hard mask layer based on the dielectric spacers. The patterns of the first and second metal lines are then transferred by an etching process to the interlevel dielectric layer as trenches in the interlevel dielectric layer. The first and second groups of the metal lines are then formed simultaneously by depositing a metal material in the trenches in the interlevel dielectric layer.

Abstract: Provided are a driver circuit, a display device and a driving method of a display panel thereof. The display device includes a source driver, a display panel, and a multiplexer. A common terminal of the multiplexer is coupled to an output terminal of a source driver channel of the source driver. The multiplexer includes a plurality of selection terminals, each coupled to a corresponding one of a plurality of data lines of the display panel. Each of the data lines has a corresponding color attribute. The color attributes of at least two of the data lines coupled to the multiplexer are a first color. The multiplexer selects each of the selection terminals once in a unit period. The multiplexer continuously selects the data lines with the same color attribute as the first color in the unit period.

Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.

Abstract: A semiconductor structure comprises: a substrate; a dielectric layer above the substrate; a second dielectric layer disposed on the dielectric layer; a metal plug disposed in the dielectric layer and comprising a nonplanar top surface of the metal plug, the nonplanar top surface of the metal plug defining a recess; and a metal rivet structure. The metal rivet structure comprises: a shaft portion penetrating the second dielectric layer and comprising a bottom surface of the shaft portion; and a head portion located in the dielectric layer and comprising a top surface of the head portion and a nonplanar bottom surface of the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the nonplanar bottom surface of the head portion mates with the nonplanar top surface of the metal plug.

Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.

Abstract: A package structure includes a package substrate, a semiconductor module on the package substrate, a package lid on the semiconductor module and attached to the package substrate, and a hybrid thermal interface material (TIM) structure between the semiconductor module and the package lid, including a TIM layer and a vapor core heat spreader in the TIM layer.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the semiconductor package via the thermal conductive bonding layer. The lid has a first cavity and a second cavity connected to the first cavity. The semiconductor package is located in the first cavity, and the thermal conductive bonding layer is partially disposed in the second cavity. The second cavity has a first portion and a second portion joined with the first portion and narrower than the first portion, the second portion is located between the first portion and the first cavity, and the thermal conductive bonding layer is formed in the second portion. A method for manufacturing a semiconductor device is also provided.

Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.

Abstract: An ionic compound, an absorbent and an absorption device are provided. The ionic compound has a structure represented by Formula (I): ABn,??Formula (I) wherein A is B is R1, R2, R3, R4, R5, and R6 are independently H, C1-6 alkyl group; and n is 1 or 2.

Abstract: Provided are a driver circuit, a display device and a driving method of a display panel thereof. The display device includes a source driver, a display panel, and a multiplexer. A common terminal of the multiplexer is coupled to an output terminal of a source driver channel of the source driver. The multiplexer includes a plurality of selection terminals, each coupled to a corresponding one of a plurality of data lines of the display panel. Each of the data lines has a corresponding color attribute. The color attributes of at least two of the data lines coupled to the multiplexer are a first color. The multiplexer selects each of the selection terminals once in a unit period. The multiplexer continuously selects the data lines with the same color attribute as the first color in the unit period.

Abstract: A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.

Abstract: An interconnection structure includes a first interconnection layer and a second interconnection layer. The first interconnection layer includes a conductive feature extending through a first dielectric layer. The second interconnection layer includes a metal contact and at least one conductive structure extending through a second dielectric layer formed over the first interconnection layer. The metal contact is configured to overlay and interconnect with the conductive feature. A portion of the conductive feature closest to the conductive structure is recessed with a depth a from a top surface of the conductive feature.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: A method includes bonding a package component to a substrate; forming a thermal interface material (TIM) over the package component; forming an adhesive layer over the substrate, the adhesive layer laterally surrounding the package component; attaching a lid to the TIM and the adhesive layer, wherein the lid has a recessed portion overlapping the TIM.

Abstract: A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate layer including a metal interconnect feature embedded in the semiconductor substrate layer and depositing a liner layer on the metal interconnect feature. The method further includes depositing an etching stop layer on the liner layer and the semiconductor substrate layer and forming a dielectric layer on the etching stop layer with a via trench to expose the etching stop layer. The method also includes etching the etching stop layer and the liner layer to form a via structure to expose the metal interconnect feature, wherein the via structure has an hourglass-shaped profile.

Abstract: Methods related to plasma processing are provided. A method includes locating a wafer on an electrostatic chuck disposed within a plasma chamber including a focus ring and a cover ring, wherein the focus ring surrounds a portion of the electrostatic chuck, and wherein the cover ring lies over the focus ring; igniting a plasma within the plasma chamber; directing a direction of ion flow toward the wafer by biasing the focus ring with a DC power source to form an electrical field; and modifying the electrical field with the cover ring, wherein an inner portion of the focus ring is blocked by the cover ring, a middle portion of the focus ring is unblocked by the cover ring, and an outer portion of the focus ring is blocked by the cover ring.

Abstract: A package structure and a formation method are provided. The method includes disposing a chip-containing structure over a substrate and forming a thermal conductive layer over the chip-containing structure. The method also includes disposing a heat-spreading lid over the chip-containing structure and the thermal conductive layer. A metallic structure is embedded in the heat-spreading lid, and the metallic structure faces the thermal conductive layer. The method further includes pressing the heat-spreading lid against the chip-containing structure at an elevated temperature such that a portion of or an entirety of the metallic structure and a portion of or an entirety of the thermal conductive layer are transformed into an intermetallic compound material.

Abstract: A method includes bonding a package component to a substrate; forming a molding compound laterally surrounding the package component; forming a thermal interface material (TIM) layer over the package component; forming a first adhesive layer over the molding compound, the first adhesive layer laterally surrounding the TIM layer; attaching a bottom surface of a lid to the TIM layer. The lid has a first trench recessed from the bottom surface thereof, a footprint of the first trench surrounds a footprint of the package component on the substrate, and a footprint of the first adhesive layer surrounds a footprint of the first trench on the substrate.