Patents by Inventor Chih-Ming Hsu

Chih-Ming Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179311
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chia-Ming TSAI, Tzu-Der CHUANG, Chih-Wei HSU, Ching-Yeh CHEN, Zhi-Yi LIN
  • Patent number: 11995471
    Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 28, 2024
    Assignee: ACER INCORPORATED
    Inventors: Kuan-Ju Chen, Wen-Cheng Hsu, Hung-Ming Chang, Chih-Wen Huang, Chao-Kuang Yang
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Publication number: 20240162313
    Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240139935
    Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
  • Publication number: 20240125299
    Abstract: An offshore wind turbine with anti-accumulation of aquatic organisms, comprising: a base with an interior space, the base being made of conductive material; a tower incorporated above the base; a nacelle, connected to the tower; a plurality of blades, each interconnected with the nacelle; and a power supply system electrically connected to the base and disposed within the interior space, the power supply system being used to provide electrical energy to the base to energize the surface of the base to form an electric field.
    Type: Application
    Filed: August 24, 2023
    Publication date: April 18, 2024
    Inventors: FU-MING TZU, CHIH-YUNG HSU
  • Patent number: 11943584
    Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 26, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Wen-Shan Lin, Nai-Hao Kuo
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Patent number: 11937415
    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Patent number: 11930174
    Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Patent number: 11916151
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
  • Patent number: 11904464
    Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: February 20, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
  • Publication number: 20230294304
    Abstract: A gripper base is provided, including a housing, a movable member, an elastic member, a position restricting mechanism, a guiding rod, and an engaging member. The elastic member is connected to the housing and the movable member. The position restricting mechanism is disposed on the movable member, and includes a groove and a block, wherein the groove surrounds the block. The groove has a top surface, and the block has an upper surface facing the top surface. The top surface has a protrusion protruding toward the block, and the upper surface has a concave structure. One end of the guiding rod is pivotally connected to the housing, and the other end of the guiding rod enters the groove. The engaging member is pivotally connected to the movable member.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 21, 2023
    Inventor: Chih-Ming HSU
  • Publication number: 20230083690
    Abstract: An electric gripper is disclosed and includes a carrier, an actuator, two dual-lever assemblies and an angle sensor. The actuator is disposed on the carrier and includes a sliding portion. The two dual-lever assemblies are disposed on the carrier and located at two opposite lateral sides of the sliding portion. Each of the two dual-lever assemblies includes a driving lever, a limiting lever and a gripping piece. The driving levers are staggered to each other. The limiting levers are staggered to each other. When the sliding portion slides a first distance in the first direction, the sliding portion drives the driving levers to rotate an angle, and the gripping pieces move toward each other to displace a second distance in a second direction. The angle sensor is disposed on the carrier and configured to measure the angle, to correspond to the first distance and the second distance.
    Type: Application
    Filed: May 11, 2022
    Publication date: March 16, 2023
    Inventors: Chih-Ming Hsu, Hsin-Hsien Wu, Shang-Wei Yang