Abstract: An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric layer, forming a work function layer over the gate dielectric layer, forming a cap over the work function layer, and forming a gate electrode layer over the cap. Forming the cap includes forming a first portion of a first capping layer over the work function layer, performing an oxygen control treatment, forming a second portion of the first capping layer over the first portion of the first capping layer, and forming a second capping layer over the first capping layer. The oxygen control treatment exposes the first portion of the first capping layer to: oxygen by breaking vacuum, ozonated deionized water, oxygen radicals, an oxygen-containing annealing environment, or a combination thereof. The first capping layer can be a metal nitride layer, and the second capping layer can be a silicon layer.

Abstract: A safety regulation verification method comprises: measuring a first transmitting power of the antenna module at a trigger distance of a proximity sensor of the mobile device; obtaining a power density design target contour based on the first transmitting power at a predetermined distance from the mobile device on a chosen surface; obtaining a distance sensing plane coverage of the proximity sensor at the predetermined distance from the mobile device on the chosen surface; comparing whether the distance sensing plane coverage surrounds the power density design target contour; and when the distance sensing plane coverage of the proximity sensor fails to surround the power density design target contour, adjusting the first transmitting power as a second transmitting power until the distance sensing plane coverage surrounds the power density design target contour.

Abstract: An electronic device is provided. The electronic device includes an antenna module and a guiding structure. The antenna module includes a plurality of antenna units and a substrate. The antenna units are arranged in a matrix on the substrate. The antenna units include a first antenna unit and a second antenna unit. The first antenna unit transmits a first wireless signal, and the second antenna unit transmits a second wireless signal. The guiding structure is formed with a plurality of guiding through-holes. The guiding through-holes correspond to the respective antenna units, and the guiding through-holes include a first guiding through-hole and a second guiding through-hole. The first guiding through-hole guides the first wireless signal primarily along a first axis, and the second guiding through-hole guides the second wireless signal primarily along a second axis. The first axis and the second axis extend outward from the substrate separately.

Abstract: A method for selecting transmit antennas and a related wireless communication device are disclosed. The wireless communication device includes an antenna array with a plurality of antennas and a control circuit. The control circuit is coupled to the antenna array and is used to determine a predetermined number of the antennas to be used for transmitting a radio frequency (RF) signal. The control circuit is further used to select, according to the predetermined number, a corresponding number of the antennas to form an activated antenna combination. In the activated antenna combination, at least two selected antennas are separated by at least one unselected antenna along a primary arrangement direction of the antenna array.

Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

Abstract: A method includes steps of: storing an entry of sensing data in a storage area of a storage module of a board management controller as sensor data; assigning a buffer area of the storage module with a locked state; copying the sensor data from the storage area to the buffer area; and assigning the buffer area with an unlocked state. A processing module of the board management controller does not respond to a request to access the sensor data when the buffer area is assigned with the locked state, and responds to the request to access the sensor data when the buffer area is assigned with the unlocked state.

Abstract: A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and an epitaxial structure beside the channel structure. The semiconductor device structure also includes a metal gate stack over the semiconductor nanostructures. The metal gate stack includes a gate dielectric layer, a first work function layer over the gate dielectric layer, and a metal oxide layer over the first work function layer. The metal oxide layer is thinner than the first work function layer. The metal gate stack also includes a second work function layer over the metal oxide layer.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.

Abstract: An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl5) and a hydrogen-comprising precursor (e.g., H2).

Abstract: A wireless communication device is provided. The wireless communication device includes a circuit board, an antenna module, a housing and a metal pattern unit. The antenna module is coupled to the circuit board, wherein the antenna module transmits a wireless signal, the antenna module defines a first FOV area and a second FOV area, and the first FOV area differs from the second FOV area. The housing covers the antenna module, wherein a lid portion of the housing corresponds to the first FOV area, and the lid portion has a first equivalent dielectric constant. The metal pattern unit corresponds to the second FOV area, the metal pattern unit causes a second equivalent dielectric constant, and the first equivalent dielectric constant differs from the second equivalent dielectric constant.

Abstract: A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.

Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

Abstract: A method for evaluating radio performance of a device under test (DUT) comprises the following steps. A first set of points, a second set of points and a third set of points are defined to locate on a sphere surrounding the DUT. A signal power of the DUT is evaluated at the first set of points to identify a first region related to the first set of points. Candidates of the second set of points are selected based on the first region. The signal power of the DUT is evaluated at the candidates of the second set of points to identify a second region related to the second set of points. Candidates of the third set of points are selected based on the second region. The signal power of the DUT is evaluated at the candidates of the third set of points to identify a beam peak.

Abstract: A multiband antenna array is provided. The multiband antenna array includes a first multi-band antenna unit, a first high band antenna member, and a first low band antenna member. The first multi-band antenna unit includes a first high band antenna element and a first low band antenna element. A first distance is formed between the center of the first multi-band antenna unit and the center of the first high band antenna member. The first distance is 0.3˜0.8 times the wavelength of a high band signal. A second distance is formed between the center of the first multi-band antenna unit and the center of the first low band antenna member. The second distance is 0.3˜0.8 times the wavelength of a low band signal.

Abstract: A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

Abstract: An autonomously activated electric energy storage device and a control method thereof are provided. The autonomously activated electric energy storage device includes a first battery cell, a second battery cell, a temperature detector, a first bidirectional charger, a second bidirectional charger and a control circuit. When the control circuit determines through the temperature detector that a battery cell temperature is equal to or lower than a low working temperature limit, the control circuit allows the first bidirectional charger to be electrically conducted with the first battery cell and the second bidirectional charger to be electrically conducted with the second battery cell, and the first battery cell and the second battery are controlled to perform power transfer therebetween through the first and the second bidirectional charger until temperatures of the first battery cell and the second battery cell are both higher than the low working temperature limit.