Patents by Inventor Chii-Ping Chen

Chii-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200118876
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a conductive line in the dielectric layer. The method also includes forming an etch stop layer over the dielectric layer and the conductive line and patterning the etch stop layer to form a contact opening exposing a portion of the conductive line. The method further includes forming a resistive layer over the etch stop layer, wherein the resistive layer extends into the contact opening. In addition, the method includes patterning the resistive layer to form a resistive element.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh HUANG, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 10515852
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Publication number: 20190279933
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
  • Patent number: 10304772
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Publication number: 20190139826
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheh HUANG, Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Chii-Ping CHEN
  • Publication number: 20190139754
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Wen-Sheh HUANG, Chii-Ping CHEN, Wan-Te CHEN
  • Patent number: 10164002
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Chii-Ping Chen, Chung-Yi Lin, Wen-Sheh Huang
  • Publication number: 20180337125
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
  • Publication number: 20180151665
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.
    Type: Application
    Filed: February 16, 2017
    Publication date: May 31, 2018
    Inventors: WAN-TE CHEN, CHUNG-HUI CHEN, CHII-PING CHEN, CHUNG-YI LIN, WEN-SHEH HUANG
  • Patent number: 9553043
    Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen, Shyue-Shyh Lin, Chii-Ping Chen
  • Patent number: 9496217
    Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yi Tsai, Chih-Hao Chen, Ming-Chung Liang, Chii-Ping Chen, Lai Chien Wen, Yuh-Jier Mii
  • Patent number: 9257279
    Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 9153484
    Abstract: A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 6, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 9147602
    Abstract: A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: September 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping Chen, Chih-Hao Chen
  • Patent number: 9003336
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Publication number: 20150044865
    Abstract: A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Chii-Ping CHEN, Chih-Hao CHEN
  • Patent number: 8847405
    Abstract: An integrated circuit which includes an interconnect structure disposed at least partially in at least one opening of a dielectric layer. The integrated circuit further includes at least one air gap disposed between the dielectric layer and the interconnect structure. The integrated circuit further includes at least one first liner material disposed under the at least one air gap, the at least one first liner material extending along a bottom portion of a sidewall of the at least one opening of the dielectric layer.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Chih-Hao Chen
  • Publication number: 20140248768
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Publication number: 20140220769
    Abstract: A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping CHEN, Dian-Hau CHEN
  • Patent number: 8716862
    Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Dian-Hau Chen