Patents by Inventor Chii-Ping Chen

Chii-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9003336
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Publication number: 20150044865
    Abstract: A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Chii-Ping CHEN, Chih-Hao CHEN
  • Patent number: 8847405
    Abstract: An integrated circuit which includes an interconnect structure disposed at least partially in at least one opening of a dielectric layer. The integrated circuit further includes at least one air gap disposed between the dielectric layer and the interconnect structure. The integrated circuit further includes at least one first liner material disposed under the at least one air gap, the at least one first liner material extending along a bottom portion of a sidewall of the at least one opening of the dielectric layer.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Chih-Hao Chen
  • Publication number: 20140248768
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Publication number: 20140220769
    Abstract: A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping CHEN, Dian-Hau CHEN
  • Patent number: 8716862
    Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 8617986
    Abstract: A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chung Liang, Chii-Ping Chen
  • Publication number: 20130260563
    Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen
  • Publication number: 20130256902
    Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung LU, Wen-Hao CHEN, Yuan-Te HOU, Fang-Yu FAN, Yu-Hsiang KAO, Dian-Hau CHEN, Shyue-Shyh LIN, Chii-Ping CHEN
  • Patent number: 8499261
    Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui Chih, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu, Chii-Ping Chen, Jiing-Feng Yang
  • Patent number: 8436473
    Abstract: An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Chih-Hao Chen
  • Patent number: 8304906
    Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20120227018
    Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Chih, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu, Chii-Ping Chen, Jiing-Feng Yang
  • Patent number: 8196072
    Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui Chih, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu, Chii-Ping Chen, Jiing-Feng Yang
  • Publication number: 20110291281
    Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20110245949
    Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Chih, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu, Chii-Ping Chen, Jiing-Feng Yang
  • Publication number: 20110215477
    Abstract: An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material.
    Type: Application
    Filed: March 5, 2010
    Publication date: September 8, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping CHEN, Chih-Hao CHEN
  • Publication number: 20110108994
    Abstract: A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: May 12, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chung LIANG, Chii-Ping CHEN
  • Publication number: 20100308469
    Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yi Tsai, Chih-Hao Chen, Ming-Chung Liang, Chii-Ping Chen, Lai Chien Wen, Yuh-Jier Mii
  • Publication number: 20100283152
    Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
    Type: Application
    Filed: April 15, 2010
    Publication date: November 11, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping CHEN, Dian-Hau CHEN