Abstract: A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured film thickness thereof before and after a first removal process, wherein the first removal process lasts a first processing duration. The controller, coupled to the processing and metrology tools, determines whether the difference between the measured film thickness and a preset film thickness exceeds a preset value, and determines a second processing duration of a second removal process according to the measured and preset film thickness and the first processing duration.

Abstract: A method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process including providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.