Patents by Inventor Chikao Ikenaga

Chikao Ikenaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160208392
    Abstract: The object of the present invention is to provide a metal plate having an excellent transportability. A maximum value of a steepness degree at a central area in a width direction of the metal plate is not more than 0.4%. In addition, the maximum value of the steepness degree at the central area is not more than a steepness degree at one end side area, and is not more than a steepness degree at the other end side area. Further, a difference between the maximum value of the steepness degree at the one end side area and the maximum value of the steepness degree at the other end side area is not more than 0.4%.
    Type: Application
    Filed: September 12, 2014
    Publication date: July 21, 2016
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Chikao IKENAGA, Isao MIYATANI
  • Publication number: 20160077303
    Abstract: There is provided a leaf spring which can prevent a reduction in the spring strength and can also prevent a reduction in the electrical conductivity when the thickness of the leaf spring is decreased. The leaf spring includes an outer frame portion an inner frame portion 5b, 11b disposed inside the outer frame portion 5a, 11a, and spring portions provided between the inner frame portion and the outer frame portion The leaf spring is made of a Cu-based alloy, and has an electrical conductivity of not less than 8% IACS and a 0.2% proof stress of not less than 900 MPa.
    Type: Application
    Filed: April 23, 2014
    Publication date: March 17, 2016
    Inventors: Yoshihiko OGINO, Chikao IKENAGA, Takahiro SAHARA, Masahiro NAGATA
  • Patent number: 8653647
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: February 18, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Publication number: 20130307000
    Abstract: A resin-attached lead frame includes a lead frame main body having a plurality of die pads (LED element resting portions) and a plurality of lead portions spaced from the die pads, the lead frame main body further including LED element resting regions each formed over an area including an upper surface of each of the die pads and an upper surface of each of the lead portions. A reflecting resin section surrounds each LED element resting region of the lead frame main body. A vapor-deposited aluminum layer or a sputtered aluminum layer is provided on respective upper surfaces of the LED element resting regions of the lead frame main body.
    Type: Application
    Filed: January 24, 2012
    Publication date: November 21, 2013
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Chikao Ikenaga, Kazunori Oda
  • Patent number: 8525351
    Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 3, 2013
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20110291303
    Abstract: A semiconductor device includes a die pad, a semiconductor element which is loaded on the die pad, and a sealing resin. A plurality of electrically conductive portions each having a layered structure including a metal foil comprising copper or a copper alloy, and electrically conductive portion plating layers provided at both upper and lower ends of the metal foil are arranged around the die pad. The die pad has a lower die pad plating layer, and the semiconductor element is loaded on the die pad comprising such a die pad plating layer. Electrodes provided on the semiconductor element are electrically connected with top ends of the electrically conductive portions via wires, respectively. The lower electrically conductive portion plating layers of the electrically conductive portions and the die pad plating layer of the die pad are exposed outside from the sealing resin on their back faces.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicants: Nitto Denko Corporation, Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 8018044
    Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: September 13, 2011
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 7947598
    Abstract: A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 24, 2011
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Shozo Ishikawa
  • Patent number: 7943427
    Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 17, 2011
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20110014752
    Abstract: A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 20, 2011
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Chikao Ikenaga, Shozo Ishikawa
  • Patent number: 7851902
    Abstract: The present invention provides a resin-sealed semiconductor device, which includes a semiconductor element; a plurality of terminal members, each surrounding the semiconductor element and including an external terminal portion, an internal terminal portion and a connecting portion; bonding wires, each connecting the semiconductor element with the internal terminal portion; and a resin-sealing portion sealing the semiconductor element, terminal members and bonding wires. Each terminal member is composed of an inner thinned portion forming the internal terminal portion and an outer thickened portion forming the external terminal portion. A rear face of each internal terminal portion, and a front face, a rear face and an outer side face of each external terminal portion are exposed to the outside from the resin-sealing portion, respectively.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: December 14, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga, Koji Tomita
  • Publication number: 20100276806
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Application
    Filed: June 30, 2010
    Publication date: November 4, 2010
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7825514
    Abstract: A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions, via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: November 2, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Shozo Ishikawa
  • Publication number: 20090174053
    Abstract: A substrate 10 for a semiconductor device includes: a base plate 1, a plurality of external terminal portions 12p, 12q, respectively arranged in a plane on the base plate 1 and having external terminal faces 12pb, 12qb respectively facing the base plate 1; a plurality of internal terminal portions 11, respectively arranged in the plane on the base plate 1 and having internal terminal faces 11a respectively facing an opposite side to the base plate 1. The internal terminal portions 11 are connected with the external terminal portions 12p, 12q, via wiring portions 17, respectively. A part of the external terminal portions 12p are located on the base plate 1 in a predetermined arrangement area A in which a semiconductor element 50 is arranged.
    Type: Application
    Filed: December 9, 2008
    Publication date: July 9, 2009
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Chikao Ikenaga, Shozo Ishikawa
  • Publication number: 20090140411
    Abstract: The present invention provides a resin-sealed semiconductor device, which includes a semiconductor element; a plurality of terminal members, each surrounding the semiconductor element and including an external terminal portion, an internal terminal portion and a connecting portion; bonding wires, each connecting the semiconductor element with the internal terminal portion; and a resin-sealing portion sealing the semiconductor element, terminal members and bonding wires. Each terminal member is composed of an inner thinned portion forming the internal terminal portion and an outer thickened portion forming the external terminal portion. A rear face of each internal terminal portion, and a front face, a rear face and an outer side face of each external terminal portion are exposed to the outside from the resin-sealing portion, respectively.
    Type: Application
    Filed: June 22, 2007
    Publication date: June 4, 2009
    Applicant: Dai Nappon Printing Co., Ltd
    Inventors: Masachika Masuda, Chikao Ikenaga, Koji Tomita
  • Publication number: 20080251902
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Application
    Filed: June 17, 2008
    Publication date: October 16, 2008
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7405468
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: July 29, 2008
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7365441
    Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: April 29, 2008
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20080048311
    Abstract: A substrate B for use in production of a semiconductor device is used, which substrate includes an adhesive sheet 50 having a base layer 51 and an adhesive layer 52, and a plurality of independently provided electrically conductive portions 20. A semiconductor element having electrodes 11 formed thereon is firmly fixed onto the substrate B, and upper portions of the plurality of electrically conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by using wires 30. The semiconductor element 10, wires 30 and electrically conductive portions 20 are sealed by using a sealing resin 40. Each of the electrically conductive portions 20 has overhanging portions 20a, and a side face 60a of the electrically conductive portion 20 is roughened, thus enhancing the joining strength between each electrically conductive portion 20 and the sealing resin 40.
    Type: Application
    Filed: July 13, 2005
    Publication date: February 28, 2008
    Applicants: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Publication number: 20070241445
    Abstract: A semiconductor device P includes a die pad 20, a semiconductor element 30 which is loaded on the die pad 20, and a sealing resin 40. A plurality of electrically conductive portions 10 each having a layered structure including a metal foil 1 comprising copper or a copper alloy, and electrically conductive portion plating layers 2 provided at both upper and lower ends of the metal foil 1 are arranged around the die pad 20. The die pad 20 has a lower die pad plating layer 2b, and the semiconductor element 30 is loaded on the die pad 20 comprising such a die pad plating layer 2b. Electrodes 30a provided on the semiconductor element 30 are electrically connected with top ends of the electrically conductive portions 10 via wires 3, respectively. The lower electrically conductive portion plating layers 2 of the electrically conductive portions 10 and the die pad plating layer 2b of the die pad 20 are exposed outside from the sealing resin 40 on their back faces.
    Type: Application
    Filed: July 13, 2005
    Publication date: October 18, 2007
    Applicants: DAI NIPPON PRINTING CO., LTD., NITTO DENKO CORPORATION
    Inventors: Chikao Ikenaga, Kentarou Seki, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura