Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.

Abstract: A method for adjusting a stitching seam for surround-view stitching is provided. A first fisheye image from a first fisheye-lens camera and a second fisheye image from a second fisheye-lens camera are received. A target object in both of the first fisheye image and the second fisheye image is detected. The first fisheye image, the second fisheye image, and the target object are projected to a stitching image, which includes a stitching seam. The adjustment direction of the stitching seam is calculated according to the distance between the target object and the first fisheye-lens camera and the distance between the target object and the second fisheye-lens camera in the stitching image. The stitching seam is adjusted according to the adjustment direction.

Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.

Abstract: A pellicle comprising a pellicle membrane with improved stability to hydrogen plasma is provided. The pellicle membrane includes a network of a plurality of carbon nanotubes. At least one carbon nanotube of the plurality of carbon nanotubes is surrounded by a multilayer protective coating that includes a stress control layer and a hydrogen permeation barrier layer over the stress control layer. The stress control layer and the hydrogen permeation barrier layer independently include an Me-containing nitride or an Me-containing oxynitride with Me selected from the group consisting of Si, Ti, Y, Hf, Zr, Zn, Mo, Cr and combinations thereof. The Me-containing nitride or the Me-containing oxynitride in the stress control layer has a first Me concentration, and the Me-containing nitride or the Me-containing oxynitride in the hydrogen permeation barrier layer has a second Me concentration less than the first Me concentration.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: Systems and method for determining a topic cohesion measurement between a content item and a hyperlinked landing page are presented. In one embodiment, a plurality of content item signals is generated for the content item and a corresponding plurality of signals are generated for the hyperlinked landing page. An analysis of the corresponding signals is conducted to determine a measurement of topic cohesion, a topic cohesion score, between the content item and the hyperlinked landing page. A cohesion predictor model is trained to generate the predictive topic cohesion score between an input content item and a hyperlinked landing page. Upon a determination that the topic cohesion score is less than a predetermined threshold, remedial actions are taken regarding the hyperlink of the content item. Alternatively, positive actions may be carried out, including promoting the content item to others, associating advertisements with the content item, and the like.

Abstract: A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.

Abstract: A method for manufacturing a high electron mobility transistor (HEMT), which comprises the following steps: providing a substrate, wherein a semiconductor layer is formed on the substrate, and a source electrode and a drain electrode are formed on the semiconductor layer; forming a passivation layer on the source electrode and the drain electrode; etching the passivation layer to form a through hole between the source electrode and the drain electrode, wherein a region of the semiconductor layer is exposed through the through hole; forming a photoresist layer on the passivation layer, wherein a first sub-region of the region of the semiconductor layer is covered by the photoresist layer, and a second sub-region of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second sub-region to form a gate electrode; and removing the passivation layer.

Abstract: In an image processing method, a detection image and a marked image are obtained. An image segmentation model is applied to segment a first segmented image from the detection image. The first segmented image is corrected according to the marked image to obtain a second segmented image. A size of the second segmented image is adjusted to obtain an adjusted segmented image. The adjusted segmented image is used as a standard segmented image of the detection image. The method improves accuracy of image segmentation and recognition.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a first source feature, a first drain feature, and a first gate structure. The second transistor includes a second source feature, a second drain feature, and a second gate structure. The first source feature is electrically coupled to the second source feature and the second drain feature is electrically coupled to the first gate structure.

Abstract: A moisture-permeable composite membrane is manufactured by the step of subjecting a mixture to a crosslinking treatment. The mixture contains a polyisoprene, a polyurethane with a polar functional group, a crosslinking agent, and a vulcanizing agent. In the mixture, a weight ratio of the polyurethane with the polar functional group to the polyisoprene ranges from 1:0.55 to 1:6.60. A method for manufacturing the moisture-permeable composite membrane is also provided.

Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A flushing switch device with automatic pressing stroke detection is provided, which is applied to the flushing switches of a toilet. The flushing switch device with automatic pressing stroke detection includes a capacitive sensor, an actuator, and a protector. The capacitive sensor senses a user's hand movements to generate a sensing signal. The actuator includes a driver and a pressing mechanism; the driver drives the pressing mechanism to press one of the flushing switches. The protector includes a detector and a controller; the detector detects a load variation during an operation of the actuator to generate a detection signal; the controller receives the sensing signal and correspondingly generates a control signal to control the actuator according to the sensing signal and the detection signal.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.

Abstract: Disclosed are some implementations of systems, apparatus, methods and computer program products for implementing a scalable computing system. The scalable computing system includes an intermediate system that facilitates communications between a core server system and a third-party system. The core server system processes a client request for a third-party service in association with a web page having a corresponding web address. The intermediate system communicates with the core server system to obtain a session token, and transmits the session token and web address to the third-party system. The third-party system may then access the web page via the web address using the session token.

Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.