Patents by Inventor Chin-An Chang

Chin-An Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149343
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20250142895
    Abstract: An embedded flash memory structure, including a semiconductor substrate, an erase gate on the semiconductor substrate, two floating gates respectively at two sides of the erase gate on the semiconductor substrate, two word lines respectively at outer sides of the two floating gates, and two metal control gates respectively on the two floating gates, wherein a sacrificial layer is at at least one side of the metal control gate, and the sacrificial layer is between the metal control gate and the erase gate or between the metal control gate and the word line.
    Type: Application
    Filed: November 30, 2023
    Publication date: May 1, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Lun Jheng, Po-Jui Chiang, Chao-Sheng Cheng, Ming-Jen Chang, Ko-Chin Chang, Yu-Ming Liu
  • Publication number: 20250118666
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: TZU PEI CHEN, MIN-HSUAN LU, HAO-HENG LIU, YUTING CHENG, HSU-KAI CHANG, PO-CHIN CHANG, OLIVIA PEI-HUA LEE, SHENG-TSUNG WANG, HUAN-CHIEH SU, SUNG-LI WANG, PINYEN LIN
  • Publication number: 20250102723
    Abstract: A display includes a light guide plate, a first optical adhesive, a light source element, and a display panel. The light guide plate includes a light guide substrate and an enhancement layer disposed on the light guide substrate. At least a portion of the enhancement layer is interposed between a first surface of the light guide substrate and the first optical adhesive. A difference between the refractive index n1 of the light guide substrate and the refractive index n2 of the at least a portion of the enhancement layer is ?n1. ?n1=n1?n2. A difference between the refractive index n3 of the first optical adhesive and the refractive index n2 of the at least a portion of the enhancement layer is ?n2. ?n2=n3?n2, ?n1?0, ?n2?0, and ?n1??n2.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Hsin-Tao Huang, Yu-Chuan Wen, Jen-Pin Yu, Ya-Chin Chang, Ching-Huan Liao
  • Patent number: 12261082
    Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Lin-Yu Huang, Shuen-Shin Liang, Sheng-Tsung Wang, Cheng-Chi Chuang, Chia-Hung Chu, Tzu Pei Chen, Yuting Cheng, Sung-Li Wang
  • Publication number: 20250086920
    Abstract: A method for adjusting a stitching seam for surround-view stitching is provided. A first fisheye image from a first fisheye-lens camera and a second fisheye image from a second fisheye-lens camera are received. A target object in both of the first fisheye image and the second fisheye image is detected. The first fisheye image, the second fisheye image, and the target object are projected to a stitching image, which includes a stitching seam. The adjustment direction of the stitching seam is calculated according to the distance between the target object and the first fisheye-lens camera and the distance between the target object and the second fisheye-lens camera in the stitching image. The stitching seam is adjusted according to the adjustment direction.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 13, 2025
    Inventors: Ziyang SONG, Chao-Chin CHANG
  • Publication number: 20250085530
    Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 13, 2025
    Inventors: Fan DONG, Chao-Chin CHANG, Ziyang SONG
  • Publication number: 20250085192
    Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 13, 2025
    Inventors: Fan DONG, Chao-Chin CHANG
  • Patent number: 12236180
    Abstract: A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Publication number: 20250063826
    Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a first source feature, a first drain feature, and a first gate structure. The second transistor includes a second source feature, a second drain feature, and a second gate structure. The first source feature is electrically coupled to the second source feature and the second drain feature is electrically coupled to the first gate structure.
    Type: Application
    Filed: November 16, 2023
    Publication date: February 20, 2025
    Inventors: Te-Chin Chang, Sheng-Jier Yang
  • Patent number: 12230507
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Patent number: 12221779
    Abstract: A flushing switch device with automatic pressing stroke detection is provided, which is applied to the flushing switches of a toilet. The flushing switch device with automatic pressing stroke detection includes a capacitive sensor, an actuator, and a protector. The capacitive sensor senses a user's hand movements to generate a sensing signal. The actuator includes a driver and a pressing mechanism; the driver drives the pressing mechanism to press one of the flushing switches. The protector includes a detector and a controller; the detector detects a load variation during an operation of the actuator to generate a detection signal; the controller receives the sensing signal and correspondingly generates a control signal to control the actuator according to the sensing signal and the detection signal.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Name Plate Co., Ltd.
    Inventors: Wen-Cheng Yin, Fu-Jung Cheng, Ho-Chuan Hsu, Yu-Hsun Tseng, Chao-Chin Chang, Kai-Li Peng
  • Patent number: 12223251
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang, Hsien-Hsin Sean Lee
  • Patent number: 12210579
    Abstract: Disclosed are some implementations of systems, apparatus, methods and computer program products for implementing a scalable computing system. The scalable computing system includes an intermediate system that facilitates communications between a core server system and a third-party system. The core server system processes a client request for a third-party service in association with a web page having a corresponding web address. The intermediate system communicates with the core server system to obtain a session token, and transmits the session token and web address to the third-party system. The third-party system may then access the web page via the web address using the session token.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 28, 2025
    Inventors: Keye Liu, Dai Duong Doan, Kaidi Xu, Angela Gu, Yi-Chin Chang, Tyler Shopshire, Shanis Kurundrayil
  • Publication number: 20250031419
    Abstract: Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: January 23, 2025
    Inventors: Kuan-Kan Hu, Po-Chin Chang, Olivia Pei-Hua Lee, Ku-Feng Yang, Sung-Li Wang, Szuya Liao
  • Publication number: 20250031365
    Abstract: A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.
    Type: Application
    Filed: August 4, 2023
    Publication date: January 23, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Hsin-Chieh Lin, Po-Jui Chiang, Pei Lun Jheng, Chao-Sheng Cheng, Ming-Jen Chang, Ko Chin Chang, Yu Ming Liu
  • Publication number: 20250022802
    Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tzu Pei Chen, Sung-Li Wang, Shin-Yi Yang, Po-Chin Chang, Yuting Cheng, Chia-Hung Chu, Chun-Hung Liao, Harry CHIEN, Chia-Hao Chang, Pinyen LIN
  • Publication number: 20250017437
    Abstract: A scraper includes a blade body defining a rear end and a front end opposite the rear end. The blade body is provided with an end face at the front end, and the end face has a first edge connected to a bottom surface and a second edge connected to an top surface opposite the bottom surface. The top surface is provided with a plurality of grooves, and each of the plurality of grooves has a first end connected to the end face and a second end extended toward the rear end. A first thickness is formed between the first edge and the second edge, and a second thickness is formed between the first edge and the first end. The second thickness is less than the first thickness. The scraper, through the aforementioned structure, can provide good scraping efficiency while maintaining good structural strength.
    Type: Application
    Filed: June 6, 2024
    Publication date: January 16, 2025
    Inventor: Chin-Chang CHIU
  • Patent number: D1070867
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 15, 2025
    Assignee: WISTRON CORP.
    Inventors: Ya Yun Chan, Po Chin Chang, Shengte Hsieh
  • Patent number: D1072834
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 29, 2025
    Assignee: WISTRON CORP.
    Inventors: Po Chin Chang, Ya Yun Chan, Shengte Hsieh