Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.

Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the isolation regions, a liner material is included between the strain material and the source and drain regions. Certain embodiments provide independent tuning of strain forces in a stacked transistor device. Different materials are selected for different layers in the stacked device to provide favorable performance enhancement or tuning (e.g., adjustment of the threshold voltage) in NMOS and PMOS layers.

Abstract: A display includes a light guide plate, a first optical adhesive, a light source element, and a display panel. The light guide plate includes a light guide substrate and an enhancement layer disposed on the light guide substrate. At least a portion of the enhancement layer is interposed between a first surface of the light guide substrate and the first optical adhesive. A difference between the refractive index n1 of the light guide substrate and the refractive index n2 of the at least a portion of the enhancement layer is ?n1. ?n1=n1?n2. A difference between the refractive index n3 of the first optical adhesive and the refractive index n2 of the at least a portion of the enhancement layer is ?n2. ?n2=n3?n2, ?n1?0, ?n2?0, and ?n1??n2.

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: Managing a battery including measuring, in response to a first charging current and over a first time period, a first amperage and a first voltage of the cell at predetermined intervals; measuring, in response to a second charging current and over a second time period, a second amperage and a second voltage of the cell at the predetermined intervals; determining that the first amperage of the cell was maintained greater than a first threshold amount of time within the first time period, and in response, qualifying the first amperage and the first voltage as stable; determining that the second amperage of the cell was maintained greater than a second threshold amount of time within the second time period, and in response, qualifying the second amperage and the second voltage as stable; and in response to the qualifying, calculating a DCIR of the cell based on the voltages and the amperage.

Abstract: A method of forming an electronic device including: providing an assembly, wherein the assembly includes a substrate, an optical film, a plurality of color filters and a defect, wherein the plurality of color filters and the defect are disposed between the substrate and the optical film; and using a laser pulse to form a first processed area that corresponds to the defect in the optical film, wherein the first processed area at least partially overlaps at least two of the plurality of color filters.

Abstract: A method for adjusting a stitching seam for surround-view stitching is provided. A first fisheye image from a first fisheye-lens camera and a second fisheye image from a second fisheye-lens camera are received. A target object in both of the first fisheye image and the second fisheye image is detected. The first fisheye image, the second fisheye image, and the target object are projected to a stitching image, which includes a stitching seam. The adjustment direction of the stitching seam is calculated according to the distance between the target object and the first fisheye-lens camera and the distance between the target object and the second fisheye-lens camera in the stitching image. The stitching seam is adjusted according to the adjustment direction.

Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.

Abstract: A pellicle comprising a pellicle membrane with improved stability to hydrogen plasma is provided. The pellicle membrane includes a network of a plurality of carbon nanotubes. At least one carbon nanotube of the plurality of carbon nanotubes is surrounded by a multilayer protective coating that includes a stress control layer and a hydrogen permeation barrier layer over the stress control layer. The stress control layer and the hydrogen permeation barrier layer independently include an Me-containing nitride or an Me-containing oxynitride with Me selected from the group consisting of Si, Ti, Y, Hf, Zr, Zn, Mo, Cr and combinations thereof. The Me-containing nitride or the Me-containing oxynitride in the stress control layer has a first Me concentration, and the Me-containing nitride or the Me-containing oxynitride in the hydrogen permeation barrier layer has a second Me concentration less than the first Me concentration.

Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.

Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: Systems and method for determining a topic cohesion measurement between a content item and a hyperlinked landing page are presented. In one embodiment, a plurality of content item signals is generated for the content item and a corresponding plurality of signals are generated for the hyperlinked landing page. An analysis of the corresponding signals is conducted to determine a measurement of topic cohesion, a topic cohesion score, between the content item and the hyperlinked landing page. A cohesion predictor model is trained to generate the predictive topic cohesion score between an input content item and a hyperlinked landing page. Upon a determination that the topic cohesion score is less than a predetermined threshold, remedial actions are taken regarding the hyperlink of the content item. Alternatively, positive actions may be carried out, including promoting the content item to others, associating advertisements with the content item, and the like.

Abstract: A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.