Patents by Inventor Chin-An Chang

Chin-An Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240390667
    Abstract: An electrode set for making a biological tissue transparent includes a first electrode and a second electrode. The first electrode and the second electrode are configured to provide an electric field for the biological tissue. The first electrode has a carrier metal and a coating metal at least partially coated on the carrier metal.
    Type: Application
    Filed: May 7, 2024
    Publication date: November 28, 2024
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: LI-AN CHU, ANN-SHYN CHIANG, TSU-CHIN CHOU, WEI-KUN CHANG, YA-HUI LIN, PEI-YUN LU
  • Patent number: 12154344
    Abstract: A method for evaluating environment and surroundings of a pedestrian passageway, used in an electronic device, obtains a position information of a target area, and obtains a streetscape image corresponding to the position information of the area. The method further inputs the streetscape image into a trained convolutional neural network, makes the trained convolutional neural network carry out a convolution calculation of the streetscape image to generate a feature vector for classifying a number of target objects in the streetscape image, and outputs the feature vector. The feature vector is input into a full convolution neural network to apply a certain color to a number of pixels belonging to a same target object, and outputs the streetscape image with colored target objects.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 26, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yueh Chang, Chin-Pin Kuo, Tzu-Chen Lin
  • Patent number: 12153039
    Abstract: Disclosed herein are methods for the detection of the presence of sperm DNA fragmentation in a semen sample. The methods include embedding of sperm cells of the semen sample in a gel, denaturing DNA of the sperm cells, and lysing the nuclear proteins of the sperm cells. The present method includes an ionic surfactant sodium dodycyl sulfate (SDS) and a chaotropic agent urea in the lysis solution for releasing DNA from protamine of chromosome, which significantly reduces the time required for lysis. A kit for detecting sperm DNA fragmentation in a semen sample is also disclosed.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: November 26, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Li-Sheng Chang, Hsiu-Chin Lee
  • Patent number: 12152917
    Abstract: A flow meter includes a meter body and a pressure sensor. The meter body has a liquid impact surface, a sensing surface opposite to the liquid impact surface, and a mounting hole extending from the sensing surface toward the liquid impact surface. The mounting hole is a blind hole. The pressure sensor is mounted in the mounting hole, and has a resistance value that can be measured and that can be changed correspondingly with a change in liquid pressure caused by a change in flow rate. A device for producing an active hydroxyl free radical solution is also disclosed.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: November 26, 2024
    Inventors: Shih-Chin Chou, Teng-Kang Chang, Chun-Ming Chen
  • Publication number: 20240387364
    Abstract: An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Publication number: 20240384405
    Abstract: A system and method for reducing thermal transfer in a dual ampoule system. The dual ampoule system includes a first ampoule, a second ampoule, and a planar heat shield. The planar heat shield is positioned between the first ampoule and the second ampoule, where the planar heat shield is configured to resist thermal transfer between the first ampoule and the second ampoule.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chi-Wen CHIU, Chih-Chang WU, Che-Wei TUNG, Chiang Hsien SHIH, Chin-Szu LEE
  • Publication number: 20240379413
    Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Chin LEE, Cherng-Shiaw TSAI, Shao-Kuan LEE, Ting-Ya LO, Chi-Lin TENG, Hsiao-Kang CHANG, Kuang-Wei YANG, Hsin-Yen HUANG, Shau-Lin SHUE
  • Publication number: 20240379333
    Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Jung-Hao Chang, Po-Chin CHANG, Pinyen LIN, Li-Te LIN
  • Publication number: 20240379758
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 14, 2024
    Inventors: Wei-Yip LOH, Hong-Mao LEE, Harry CHIEN, Po-Chin CHANG, Sung-Li WANG, Jhih-Rong HUANG, Tzer-Min SHEN, Chih-Wei CHANG
  • Publication number: 20240379416
    Abstract: A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Publication number: 20240379435
    Abstract: A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Kuan LEE, Cheng-Chin LEE, Cherng-Shiaw TSAI, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12142220
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: November 12, 2024
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Patent number: 12142845
    Abstract: The present disclosure relates to a compact antenna system within a dielectric housing of an electronic device, capable of achieving improved reflection performance. The antenna system includes a ground plane and an antenna PCB. An antenna microstrip feed on a side of the antenna PCB comprises a first part of a radiating antenna element. The antenna PCB is connected to the ground plane by a central conductor of a coaxial cable which forms a ground path. An outer conductor of the coaxial cable carries RF signals to the antenna PCB, allowing the RF signals to freely radiate along a length of the coaxial cable and acting as a second part of the radiating antenna element. The coaxial cable does not interfere with, and can even enhance a radiation pattern of the antenna microstrip feed.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 12, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yung-Chang Wei, Chin-Hung Ma, I-Chen Lin, Po Chao Chen
  • Patent number: 12143823
    Abstract: A method for implementing requests from an app by a SIM in a mobile phone comprises the steps of: binding an app to a BIP server by a mobile phone; delivering a request command to the BIP server from the mobile phone; converting the request command to an APDU format, packing the converted request command in the APDU format in a request packet, and delivering the request packet to an IP of a SIM by the BIP server; receiving and unpacking the request packet to have the converted request command, and providing the converted request command to the SIM; executing the request command to have a result by the SIM; delivering the result in a response packet to the BIP server via the mobile network relayed; unpacking the response packet to fetch the result, and delivering the result to the mobile phone for the app by the BIP server.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: November 12, 2024
    Assignee: Taisys Technologies Co., Ltd.
    Inventors: Chun Hsin Ho, Chih Nung Wang, Chien Chou Chen, Chin Chang Wu
  • Publication number: 20240372344
    Abstract: A power supply has a housing, a circuit board, a wire, and a wire securing assembly. The wire securing assembly has a base plate and a securing structure. The securing structure has a first plate and a second plate. A side edge of the first plate is connected to the base plate. The second plate is spaced apart from the first plate. The wire is mounted through and between the first plate and the second plate. The wire securing assembly is modified from the current insulating part, in which the original side plate extends and forms an additional part, or a bent structure is added on the original side plate, and thus the additional structures become the securing structure. Thus, the wire is prevented from moving under vibration or external force and contacting the blades of the fan, or keeps in a position in compliance with safety requirements.
    Type: Application
    Filed: November 9, 2023
    Publication date: November 7, 2024
    Inventors: Cheng-Chia LIN, Yueh-Feng LI, Yu-Hsuan TING, Nung-Chin KAO, Chih-Wei CHANG
  • Publication number: 20240371764
    Abstract: An interconnect structure includes a dielectric layer, a conductive feature, a conductive layer, a capping layer, a support layer and an etch stop layer. The conductive feature is disposed in the dielectric layer. A first portion of the conductive layer is disposed over the first conductive feature, and a second portion of the conductive layer is disposed over the dielectric layer. A first portion of the capping layer is in contact with the first portion of the conductive layer, a second portion of the capping layer is in contact with the second portion of the conductive layer, and a third portion of the capping layer is in contact with the dielectric layer. An air gap is defined by the support layer and the capping layer. The etch stop layer is disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Hsin-Yen HUANG, Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cheng-Chin LEE, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12136650
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: November 5, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Wen Hsiung, Chun-Lung Chang, Kun-Huang Yu, Kuo-Chin Chiu, Wu-Te Weng
  • Publication number: 20240363528
    Abstract: A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The first dielectric layer is disposed on the substrate. The conductive feature is formed in the first dielectric layer and is electrically connected to the conductive structure. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Shao-Kuan LEE, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Publication number: 20240363721
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin CHANG, Ming-Huan TSAI, Li-Te LIN, Pinyen LIN
  • Publication number: 20240363400
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE