Patents by Inventor Chin-An Chang

Chin-An Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736979
    Abstract: A data packet transmission method—that includes: obtaining, by a terminal, N application programs that are running; and if the N application programs include an application program including a low-latency service; determining whether an unlicensed frequency band is in a congestion state; and instructing a network device to schedule a data packet of the terminal to a licensed frequency band for transmission when the unlicensed frequency band is in a congestion state. When determining that the N running application programs include the application program including the low-latency service, the terminal may instruct the network device to schedule the data packet of the terminal to the licensed frequency band for transmission, so as to transmit a data packet of the low-latency service by using the licensed frequency band. Resources in the licensed frequency band are centrally scheduled by the network device, instead of being used through contention.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 22, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuan-Hao Lan, Fei Yin, Yuxin Yang, Te-Chin Chang, Haw-Wei Shu
  • Publication number: 20230260803
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20230253308
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Yuting CHENG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Pinyen LIN, Sung-Li WANG, Sheng-Tsung WANG, Lin-Yu HUANG, Shao-An WANG, Harry CHIEN
  • Patent number: 11722536
    Abstract: Various embodiments of the present disclosure provide for generating, updating, and/or otherwise managing a shared dynamic collaborative presentation progression interface in association with an audio-video conferencing interface service. An example embodiment is configured to monitor an active audio-video conference presentation that is configured for display to participating client devices by the audio-video conference interface service, generate a shared dynamic collaborative presentation progression interface, transmit the shared dynamic collaborative presentation progression interface to the plurality of participating client devices, receive an initiate topic object sequence set event from at least one participating client device of the participating client devices, identify a first topic object of the topic object sequence set as an active topic object, and update the shared dynamic collaborative presentation progression interface render an active visual emphasis element of the first topic object.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: August 8, 2023
    Assignees: ATLASSIAN PTY LTD., ATLASSIAN, INC.
    Inventors: Ryan Crumley, Matthew McDaniel, Shiuan-chin Chang, Dylan Soechting
  • Publication number: 20230246089
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Patent number: 11714946
    Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Yang, Hsien-Hsin Sean Lee
  • Publication number: 20230230916
    Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN
  • Patent number: 11703966
    Abstract: A touch display module includes a touch device and a polarizing element. The polarizing element includes a polarizer and a retardation film assembly. The retardation film assembly has a polarization ellipticity value (e-value), and the absolute value of the e-value is greater than 0.8. A reflection rate of the polarizing element is less than 6%, and a total reflection rate of the touch device and the polarizing element is less than 7%.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 18, 2023
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Ming Chung Liu, Yi Lung Yang, Ya Chin Chang, Po Yu Hsiao, Sheng Fa Liu, Wei Chou Chen, Xue Fen Wang, Yong Bin Ke, Chia Jui Lin, Shao Jie Liu, Xue Long Zhang, Xian Bin Xu
  • Patent number: 11698191
    Abstract: An ignition method of a plasma chamber includes steps of: (a) starting softly an ignition voltage to a first voltage, (b) decreasing the magnitude of the ignition voltage to a second voltage after a first ignition time, (c) increasing the magnitude of the ignition voltage to the first voltage after a second ignition time, and (d) repeating the step (b) and the step (c) until the ignition is successful.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: July 11, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Kun-Han Yang, Chin-Chang Kuo, Wei-Hsun Lai
  • Publication number: 20230212046
    Abstract: A microbial carrier and a device for treating wastewater are provided. The microbial carrier includes a bacteriophilic material and a plurality of foam cells, wherein the foam cells are disposed in the bacteriophilic material. The bactericidal material is a reaction product of a composite, wherein the composition includes a hydrophobic polyvinyl alcohol and a cross-linking agent, wherein the surface energy of the hydrophobic polyvinyl alcohol is 30 mJ/m2 to 58 mJ/m2.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Ting CHANG, Kuan-Foo CHANG, Cheng-Chin CHANG, Yi-Chun LIU, Mei-Chih PENG
  • Publication number: 20230208895
    Abstract: Various embodiments of the present disclosure provide for generating, updating, and/or otherwise managing a shared dynamic collaborative presentation progression interface in association with an audio-video conferencing interface service. An example embodiment is configured to monitor an active audio-video conference presentation that is configured for display to participating client devices by the audio-video conference interface service, generate a shared dynamic collaborative presentation progression interface, transmit the shared dynamic collaborative presentation progression interface to the plurality of participating client devices, receive an initiate topic object sequence set event from at least one participating client device of the participating client devices, identify a first topic object of the topic object sequence set as an active topic object, and update the shared dynamic collaborative presentation progression interface render an active visual emphasis element of the first topic object.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: Ryan CRUMLEY, Matthew MCDANIEL, Shiuan-chin CHANG, Dylan SOECHTING
  • Patent number: 11690171
    Abstract: A conductive bump electrode structure includes a substrate, an elastic circuit layer, at least two conductive bumps, and an insulating layer. The elastic circuit layer is mounted on the substrate, and includes at least one elastic circuit. The at least two conductive bumps are mounted on the elastic circuit layer, and are electrically connected to each other through the at least one elastic circuit. The insulating layer is mounted on the elastic circuit layer, and includes at least two holes. Since there is a gap between the conductive bumps, the conductive bump electrode structure is easy to be bent and fit body curves of various parts of a user. The elastic circuit can stretch or compress along with the user's movement due to its elasticity, thereby increasing suitability of the conductive bump electrode structure to the human body.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: June 27, 2023
    Assignee: SINGULAR WINGS MEDICAL CO., LTD.
    Inventors: Chin-Chang Liao, Jheng-Fen Guo
  • Patent number: 11681850
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
  • Publication number: 20230171245
    Abstract: Disclosed are some implementations of systems, apparatus, methods and computer program products for implementing a scalable computing system. The scalable computing system includes an intermediate system that facilitates communications between a core server system and a third-party system. The core server system processes a client request for a third-party service in association with a web page having a corresponding web address. The intermediate system communicates with the core server system to obtain a session token, and transmits the session token and web address to the third-party system. The third-party system may then access the web page via the web address using the session token.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Applicant: Salesforce.com, Inc.
    Inventors: Keye Liu, Dai Duong Doan, Kaidi Xu, Angela Gu, Yi-Chin Chang, Tyler Shopshire, Shanis Kurundrayil
  • Publication number: 20230155005
    Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.
    Type: Application
    Filed: May 13, 2022
    Publication date: May 18, 2023
    Inventors: Yu-Lien Huang, Hao-Heng Liu, Po-Chin Chang, Yi-Shan Chen, Ming-Huan Tsai
  • Patent number: 11652152
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Ming-Huan Tsai, Li-Te Lin, Pinyen Lin
  • Patent number: 11651972
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Patent number: 11641546
    Abstract: A method for minimizing post-playback oscillation during playback of a haptic playback waveform to a haptic transducer may include determining whether a frequency response of the haptic playback waveform has a notch with a notch frequency at approximately a resonant frequency of the haptic transducer and, responsive to the notch frequency differing from the resonant frequency, modifying the haptic playback waveform for playback to the haptic transducer by shifting the notch frequency to approximately the resonant frequency.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 2, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Kok Chin Chang, Marco Janko, Kyle Wilkinson
  • Patent number: 11626506
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Publication number: 20230107847
    Abstract: A semiconductor die may include metal interconnect structures located within interconnect-level dielectric material layers, bonding pads located on a topmost interconnect-level dielectric material layer, a dielectric passivation layer located on the topmost interconnect-level dielectric material layer, and metal bump structures extending through the dielectric passivation layer and located on the bonding pads. Each of the metal bump structures comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads, a tapered surface segment in contact with a tapered sidewall of a respective opening through the dielectric passivation layer, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the bonding pads.
    Type: Application
    Filed: May 19, 2022
    Publication date: April 6, 2023
    Inventors: Yen-Kun LAI, Yi-Wen WU, Kuo-Chin CHANG, Po-Hao TSAI, Mirng-Ji LII