Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.

Abstract: A disaster information providing apparatus includes a memory that stores words and images corresponding to each other, a communication interface configured to receive a notification message, a processor configured to determine whether the notification message includes a predetermined word, and when the notification message includes the predetermined word, extract a predetermined image corresponding to the predetermined word from the memory, and a display that displays the predetermined image.

Abstract: An ignition method of a plasma chamber includes steps of: (a) starting softly an ignition voltage to a first voltage, (b) decreasing the magnitude of the ignition voltage to a second voltage after a first ignition time, (c) increasing the magnitude of the ignition voltage to the first voltage after a second ignition time, and (d) repeating the step (b) and the step (c) until the ignition is successful.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.

Abstract: A shutter with a dimming capability has a frame member, a first shutter body, and a second shutter body. The first shutter body has a plurality of through apertures on a surface and at least one magnetic member disposed along two sides of the through apertures. A height of the second shutter body is shorter than a height of the first shutter body, and the second shutter body further has a plurality of horizontal channels on a surface and at least one magnet member disposed along the horizontal channels. An area of the magnet member is smaller than an area of the magnetic member. The first and second shutter bodies are combinable via the magnetic member and the magnet member and slidably mounted in the frame member such that the second shutter body is movable in the frame member.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: A method for preparing a supported carbon catalyst, the method includes at least the following steps: contacting a gas containing an organic silicon source with a silicon oxide-based material to obtain a precursor; contacting the precursor with a gas containing an organic carbon source to obtain the supported carbon catalyst. The temperature and energy consumption of the chemical vapor deposition of heteroatom-containing carbon material on silica-based materials can be greatly reduced in this method, and the cost of the catalyst can be effectively reduced.

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A method for producing biodiesel and triacetin includes steps as follows. A bio-oil source is provided; the bio-oil source is palm oil acid or palm oil sludge. A bio-oil source pretreatment step is performed, wherein the bio-oil source is mixed with ash to decolor. A pre-esterification step is performed, wherein methanol and a pre-esterification catalyst are mixed, so as to form an organic phase solution and an aqueous phase solution. A transesterification step is performed, wherein the methanol and a lithium silicate catalyst are mixed, so as to form a crude biodiesel phase solution and a crude glycerol phase solution. A washing step is performed, wherein purified biodiesel is collected. A glycerol separating step is performed, wherein purified glycerol is collected. A glycerol esterification step is performed, wherein triacetin is collected.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A WI-FI hotspot recommendation method includes scanning a WI-FI hotspot, determining an Internet-accessible hotspot in WI-FI hotspots that are obtained by means of scanning, determining network quality obtained when the terminal accesses a network by using the Internet-accessible hotspot, and displaying an identifier of the Internet-accessible hotspot and an identifier that indicates the network quality obtained when the terminal accesses the network by using the Internet-accessible hotspot.

Abstract: A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.

Abstract: This application provides a data service method relates to the field of communications technologies, the method comprises: a first router is connected to a second router, and the first router establishes a connection to the Internet. The terminal establishes a wireless local area network connection to the second router. A terminal broadcasts request information for obtaining a network configuration parameter. The terminal receives and stores a first network configuration parameter and a second network configuration parameter respectively sent by the first router and the second router; and determines a network configuration parameter used for network configuration. The second router receives a second data service request sent by the terminal, and forwards the request to the first router, so that the first router sends the request to a server through the Internet, thereby implementing a second data service of the terminal.

Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.

Abstract: A table saw includes a base assembly; a table assembly mounted on the base assembly and comprising a table and a circular saw blade; a rip fence assembly moveably disposed on one end of the table assembly; and a slide mechanism mounted on the table assembly and including front and rear tracks affixed to front end rear ends of the table respectively; front and rear slides each having one end secured to either end of the rip fence assembly and the other end being open wherein the front and rear slides are moveably mounted on the front and rear tracks respectively; and first, second, third, fourth, and fifth rollers disposed in each of the front and rear tracks. The first, second, fourth, and fifth rollers are at an elevation higher than that of the third roller.