Abstract: A mineral oil based coolant for immersion cooling systems, which contains polyalphaolefins and a modifier that lower the viscosity of the polyalphaolefins when mixed with the polyalphaolefins. The polyalphaolefins comprises poly(1-decene). The modifier comprises one or more fatty alcohols. The one or more fatty alcohols comprises four-seven carbon fatty alcohols. The four-seven carbon fatty alcohols comprise butanol or heptanol. The modifier comprises one or more fatty acids.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A contiguous memory allocation device includes a memory and a processor. The memory is configured to store at least one command. The processor is configured to read the at least one command to execute following steps: calculating a page thrashing value of the memory; determining a corresponding relation between the page thrashing value and a predetermined thrashing value; and deciding whether to lend a contiguous memory according to the corresponding relation.

Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.

Abstract: A pixel array substrate including a substrate and multiple pixel units is provided. The pixel units are disposed on the substrate, and each include at least one active device, a pixel electrode and at least one storage capacitor. The pixel electrode is electrically connected to the at least one active device, and has multiple openings. The at least one storage capacitor is electrically connected to the pixel electrode and the at least one active device. The at least on storage capacitor completely overlaps a part of the openings of the pixel electrode. An electrowetting display panel adopting the pixel array substrate is also provided.

Abstract: A composite material and a method for manufacturing the composite material are provided. The composite material includes a laminated structure formed by co-extruding a thermoplastic elastomer and a modified thermoplastic elastomer. The use of the thermoplastic elastomer and the modified thermoplastic elastomer in the composite material can significantly reduce emissions during the manufacturing process, and the manufacturing process is simple and stable, and can improve the wear resistance of the composite material.

Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.

Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: A metal layer of a semiconductor device may be included in an extreme low dielectric constant (ELK) dielectric layer in an interconnect structure of the semiconductor device. The metal layer may be coupled with a bonding via that extends through a silicon carbide (SiC) layer in a bonding region of the semiconductor device. The ELK dielectric layer and/or the silicon carbide layer reduces stress migration in the semiconductor relative to the use of other dielectric materials such as silicon nitride and/or silicon glass. The ELK dielectric layer and/or the silicon carbide layer also reduces resistance-capacitance (RC) delay in the interconnect structure relative to the use of other dielectric materials. The ELK dielectric layer and/or the silicon carbide layer provides improved adhesion with the metal material(s) (e.g., copper and/or another metal material) of the metal layer and/or of the bonding via coupled with the metal layer.

Abstract: A transparent display apparatus includes a first transparent substrate, first to third light-emitting elements, and a first frequency band blocking filter. The first transparent substrate has a first display area and a first transparent area outside the first display area. The first to third light-emitting elements are disposed at the first display area and respectively used for emitting first to third color lights. The first frequency band blocking filter is disposed on a transmission path of the first to third color lights. The first frequency band blocking filter has first to third blocking bands respectively corresponding to the first to third color lights. FWHM of the first to third blocking bands fall in a range of 15 nm to 55 nm.

Abstract: A mouse device is provided. The mouse device includes a battery module, a casing, and a control circuit. The battery module includes a first connection interface. The casing includes a second connection interface. The control circuit is disposed inside the casing and is electrically connected to the second connection interface. The battery module is detachably mated with the second connection interface through the first connection interface, and the battery module is exposed outside of the casing when being mated with the second connection interface. The control circuit obtains a power supply from the battery module through the second connection interface when the battery module is mated with the second connection interface.

Abstract: A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.

Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.

Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: A controller integrated circuit (IC) and a method for controlling a storage device for a host device to enhance overall performance are provided. The host device may include the controller IC, where the storage device is positioned outside the host device. The controller IC may include a plurality of first queues, a first queue notification register and a first queue auxiliary notification register, where each first queue of the first queues is arranged to queue first queue entries for being used to interact with the storage device. The first queue notification register may store first queue notification information for indicating whether any first queue of the plurality of first queues sends any first interrupt. The first queue auxiliary notification register may store first queue auxiliary notification information for indicating which first queue of the plurality of first queues is the any first queue that has sent the any first interrupt.