Abstract: In an example, a power plug may include a connector to engage with a power receptacle of an electronic device, and a removable lock ring disposed around the connector. The lock ring may include a lock tab disposed on the lock ring and extending in a direction away from a longitudinal axis of the power plug. The lock tab may insert into a lock notch of the power receptacle.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.

Abstract: A scale assembly of a table saw includes front and rear outer slide members at front and rear ends of a slide mechanism respectively; front and rear inner slide members at front and rear ends of a table assembly respectively in which the front inner slide member slides in the front outer slide member and the rear inner slide member slides in the rear outer slide member; a block member secured to a front end of a rip fence assembly and including a channel and a spring biased member; and a lever in the channel and including a trigger, a projection, and first and second recesses in which in a locked position, the spring biased member is biased by a spring to enter the first recess and the projection enters a lengthwise cavity on an outer surface of the front outer slide member.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: A conductive bump electrode structure includes a substrate, an elastic circuit layer, at least two conductive bumps, and an insulating layer. The elastic circuit layer is mounted on the substrate, and includes at least one elastic circuit. The at least two conductive bumps are mounted on the elastic circuit layer, and are electrically connected to each other through the at least one elastic circuit. The insulating layer is mounted on the elastic circuit layer, and includes at least two holes. Since there is a gap between the conductive bumps, the conductive bump electrode structure is easy to be bent and fit body curves of various parts of a user. The elastic circuit can stretch or compress along with the user's movement due to its elasticity, thereby increasing suitability of the conductive bump electrode structure to the human body.

Abstract: The present invention is a pallet strapping device having a platform, a lower guiding strap portion, an upper guiding strap portion, a first frame portion, a second frame portion and a central guiding strap portion. By controlling a first guiding strap portion, a second guiding strap portion, and the central guiding strap portion that is moved to a retracted position, a first guiding strap circulation path can be formed. In addition, by controlling the first frame portion, the second frame portion and the central guiding strap portion that is moved to an extended position, a second guiding strap circulation path is formed. The present invention is capable of switching to different strapping paths corresponding to different pallets for strapping. Besides, it is quite convenient to conduct strapping tasks under the condition that the corresponding pallets is not needed to depart from the platform of the pallet strapping device.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.

Abstract: A disaster information providing apparatus includes a memory that stores words and images corresponding to each other, a communication interface configured to receive a notification message, a processor configured to determine whether the notification message includes a predetermined word, and when the notification message includes the predetermined word, extract a predetermined image corresponding to the predetermined word from the memory, and a display that displays the predetermined image.

Abstract: An ignition method of a plasma chamber includes steps of: (a) starting softly an ignition voltage to a first voltage, (b) decreasing the magnitude of the ignition voltage to a second voltage after a first ignition time, (c) increasing the magnitude of the ignition voltage to the first voltage after a second ignition time, and (d) repeating the step (b) and the step (c) until the ignition is successful.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.

Abstract: A shutter with a dimming capability has a frame member, a first shutter body, and a second shutter body. The first shutter body has a plurality of through apertures on a surface and at least one magnetic member disposed along two sides of the through apertures. A height of the second shutter body is shorter than a height of the first shutter body, and the second shutter body further has a plurality of horizontal channels on a surface and at least one magnet member disposed along the horizontal channels. An area of the magnet member is smaller than an area of the magnetic member. The first and second shutter bodies are combinable via the magnetic member and the magnet member and slidably mounted in the frame member such that the second shutter body is movable in the frame member.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: A semiconductor device includes a first cell. The first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. The semiconductor device further includes a second cell abutting the first cell. The second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.

Abstract: A method for preparing a supported carbon catalyst, the method includes at least the following steps: contacting a gas containing an organic silicon source with a silicon oxide-based material to obtain a precursor; contacting the precursor with a gas containing an organic carbon source to obtain the supported carbon catalyst. The temperature and energy consumption of the chemical vapor deposition of heteroatom-containing carbon material on silica-based materials can be greatly reduced in this method, and the cost of the catalyst can be effectively reduced.

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.